Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1873978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40171012

1

T4

4984

T5

7354

T6

4032

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29156681	1			T4	1684		T5	2024		T6	1246
values[0x0]	11445377	1			T4	3300		T5	5330		T6	2786
values[0x1]	1442932	1			T4	206		T5	242		T6	195

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	566201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41478789

1

T4

5190

T5

7596

T6

4227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19966750	1			T4	2595		T5	3799		T6	2114
valid_sources[0x01]	19965464	1			T4	2595		T5	3797		T6	2113
valid_sources[0x02]	33428	1			T76	1		T530	470		T145	107
valid_sources[0x03]	33680	1			T32	4		T530	527		T145	79
valid_sources[0x04]	39486	1			T32	2		T198	16		T530	483
valid_sources[0x05]	34515	1			T530	479		T145	69		T533	14
valid_sources[0x06]	33430	1			T76	3		T197	1		T530	572
valid_sources[0x07]	33479	1			T197	2		T198	2		T530	539
valid_sources[0x08]	33316	1			T530	506		T145	94		T533	6
valid_sources[0x09]	34465	1			T32	3		T76	2		T530	506
valid_sources[0x0a]	33494	1			T76	3		T197	3		T530	448
valid_sources[0x0b]	34004	1			T32	1		T76	1		T197	2
valid_sources[0x0c]	33935	1			T530	574		T145	85		T533	18
valid_sources[0x0d]	33725	1			T530	531		T145	87		T533	33
valid_sources[0x0e]	34275	1			T76	2		T530	537		T145	91
valid_sources[0x0f]	34004	1			T32	5		T197	2		T530	521
valid_sources[0x10]	34096	1			T530	525		T145	92		T533	6
valid_sources[0x11]	33496	1			T198	8		T530	584		T145	75
valid_sources[0x12]	33939	1			T197	1		T530	471		T145	93
valid_sources[0x13]	33920	1			T32	1		T76	1		T530	504
valid_sources[0x14]	33569	1			T32	3		T76	1		T530	509
valid_sources[0x15]	33868	1			T32	4		T76	1		T530	497
valid_sources[0x16]	34675	1			T197	2		T530	574		T145	106
valid_sources[0x17]	34295	1			T32	3		T198	7		T530	525
valid_sources[0x18]	34417	1			T197	2		T198	4		T530	509
valid_sources[0x19]	34351	1			T76	1		T197	2		T530	465
valid_sources[0x1a]	33598	1			T76	1		T197	1		T530	467
valid_sources[0x1b]	33491	1			T530	508		T145	89		T533	7
valid_sources[0x1c]	34076	1			T2	39		T197	1		T530	458
valid_sources[0x1d]	33477	1			T76	1		T530	449		T145	86
valid_sources[0x1e]	33556	1			T32	3		T197	1		T530	496
valid_sources[0x1f]	33891	1			T76	1		T530	504		T145	94
valid_sources[0x20]	33622	1			T76	1		T530	479		T145	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28527802

1

T4

1684

T5

2024

T6

1246

values[0x0]

all_enables

biggest_size

11407122

1

T4

3300

T5

5330

T6

2786

values[0x1]

all_enables

biggest_size

236088

1

T32

20

T2

16

T76

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2892439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455943

1

T72

16

T73

584

T74

567

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133051	1			T72	48		T73	1460		T74	1298
values[0x0]	1081749	1			T72	8		T73	1443		T74	1323
values[0x1]	1133582	1			T72	55		T73	1482		T74	1339

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2240190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1108192

1

T72

47

T73

1430

T74

1310

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51928	1			T72	5		T73	61		T74	68
valid_sources[0x01]	51721	1			T72	3		T73	65		T74	53
valid_sources[0x02]	51668	1			T73	73		T74	56		T78	2
valid_sources[0x03]	52923	1			T72	3		T73	69		T74	65
valid_sources[0x04]	52489	1			T73	54		T74	69		T78	3
valid_sources[0x05]	52620	1			T72	1		T73	79		T74	60
valid_sources[0x06]	52620	1			T72	5		T73	61		T74	64
valid_sources[0x07]	51931	1			T72	6		T73	64		T74	54
valid_sources[0x08]	52568	1			T72	2		T73	67		T74	62
valid_sources[0x09]	52846	1			T73	73		T74	59		T77	17
valid_sources[0x0a]	51888	1			T72	1		T73	81		T74	64
valid_sources[0x0b]	52590	1			T72	1		T73	84		T74	70
valid_sources[0x0c]	52048	1			T73	72		T74	62		T77	12
valid_sources[0x0d]	52651	1			T72	3		T73	73		T74	64
valid_sources[0x0e]	53066	1			T73	68		T74	67		T78	3
valid_sources[0x0f]	52381	1			T72	1		T73	74		T74	64
valid_sources[0x10]	51768	1			T72	9		T73	65		T74	52
valid_sources[0x11]	52628	1			T72	4		T73	68		T74	56
valid_sources[0x12]	51694	1			T72	3		T73	66		T74	57
valid_sources[0x13]	53229	1			T72	3		T73	67		T74	64
valid_sources[0x14]	52432	1			T72	1		T73	76		T74	78
valid_sources[0x15]	53477	1			T72	1		T73	58		T74	79
valid_sources[0x16]	51575	1			T73	69		T74	67		T79	3
valid_sources[0x17]	51051	1			T72	1		T73	74		T74	63
valid_sources[0x18]	52262	1			T72	1		T73	67		T74	50
valid_sources[0x19]	52947	1			T72	1		T73	68		T74	58
valid_sources[0x1a]	52666	1			T72	1		T73	73		T74	74
valid_sources[0x1b]	51612	1			T72	1		T73	78		T74	62
valid_sources[0x1c]	52578	1			T72	3		T73	71		T74	69
valid_sources[0x1d]	51182	1			T73	60		T74	71		T78	5
valid_sources[0x1e]	53222	1			T72	3		T73	68		T74	59
valid_sources[0x1f]	53760	1			T72	4		T73	60		T74	60
valid_sources[0x20]	53800	1			T72	1		T73	64		T74	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47459

1

T72

9

T73

47

T74

58

values[0x0]

all_enables

biggest_size

360635

1

T72

3

T73

466

T74

443

values[0x1]

all_enables

biggest_size

47849

1

T72

4

T73

71

T74

66

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3082634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

501087

1

T72

18

T73

672

T74

549

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1229326	1			T72	107		T73	1576		T74	1394
values[0x0]	1129842	1			T72	16		T73	1503		T74	1222
values[0x1]	1224553	1			T72	97		T73	1547		T74	1429

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2365997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1217724

1

T72

88

T73

1548

T74

1394

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55502	1			T72	7		T73	78		T74	59
valid_sources[0x01]	55724	1			T72	5		T73	83		T74	61
valid_sources[0x02]	56748	1			T72	2		T73	80		T74	74
valid_sources[0x03]	56995	1			T72	1		T73	80		T74	71
valid_sources[0x04]	56030	1			T72	1		T73	75		T74	58
valid_sources[0x05]	56706	1			T72	2		T73	82		T74	64
valid_sources[0x06]	55997	1			T72	2		T73	84		T74	68
valid_sources[0x07]	55489	1			T72	3		T73	68		T74	57
valid_sources[0x08]	56906	1			T72	10		T73	58		T74	76
valid_sources[0x09]	55182	1			T72	4		T73	76		T74	64
valid_sources[0x0a]	55048	1			T72	5		T73	71		T74	62
valid_sources[0x0b]	56456	1			T72	3		T73	76		T74	62
valid_sources[0x0c]	55498	1			T72	7		T73	62		T74	70
valid_sources[0x0d]	55736	1			T72	5		T73	57		T74	58
valid_sources[0x0e]	57030	1			T72	7		T73	91		T74	58
valid_sources[0x0f]	55194	1			T73	74		T74	49		T77	3
valid_sources[0x10]	56014	1			T72	3		T73	64		T74	70
valid_sources[0x11]	55113	1			T72	4		T73	64		T74	57
valid_sources[0x12]	56044	1			T72	1		T73	90		T74	65
valid_sources[0x13]	57003	1			T72	4		T73	79		T74	60
valid_sources[0x14]	55961	1			T72	4		T73	57		T74	62
valid_sources[0x15]	56229	1			T72	2		T73	60		T74	72
valid_sources[0x16]	55597	1			T72	4		T73	59		T74	62
valid_sources[0x17]	55978	1			T72	6		T73	55		T74	70
valid_sources[0x18]	55515	1			T72	1		T73	58		T74	70
valid_sources[0x19]	55041	1			T72	1		T73	84		T74	52
valid_sources[0x1a]	55547	1			T72	2		T73	76		T74	82
valid_sources[0x1b]	55736	1			T72	5		T73	76		T74	62
valid_sources[0x1c]	56659	1			T72	2		T73	58		T74	55
valid_sources[0x1d]	55095	1			T72	5		T73	87		T74	64
valid_sources[0x1e]	56224	1			T72	2		T73	78		T74	59
valid_sources[0x1f]	56472	1			T72	3		T73	58		T74	65
valid_sources[0x20]	54824	1			T72	2		T73	49		T74	69

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52758

1

T72

5

T73

75

T74

57

values[0x0]

all_enables

biggest_size

395738

1

T72

6

T73

516

T74

436

values[0x1]

all_enables

biggest_size

52591

1

T72

7

T73

81

T74

56

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2913054	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461224

1

T72

10

T73

619

T74

527

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1141803	1			T72	50		T73	1508		T74	1333
values[0x0]	1089696	1			T72	4		T73	1454		T74	1354
values[0x1]	1142779	1			T72	49		T73	1445		T74	1371

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2255106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1119172

1

T72

37

T73

1454

T74

1298

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52946	1			T72	1		T73	83		T74	65
valid_sources[0x01]	51877	1			T72	3		T73	73		T74	38
valid_sources[0x02]	52929	1			T72	2		T73	73		T74	75
valid_sources[0x03]	52885	1			T73	80		T74	49		T77	2
valid_sources[0x04]	52233	1			T72	1		T73	59		T74	71
valid_sources[0x05]	53888	1			T72	2		T73	72		T74	72
valid_sources[0x06]	53016	1			T73	61		T74	50		T79	2
valid_sources[0x07]	51974	1			T72	2		T73	80		T74	72
valid_sources[0x08]	53210	1			T72	1		T73	87		T74	62
valid_sources[0x09]	51809	1			T72	1		T73	81		T74	42
valid_sources[0x0a]	52669	1			T72	3		T73	56		T74	61
valid_sources[0x0b]	53109	1			T72	2		T73	73		T74	59
valid_sources[0x0c]	52006	1			T72	4		T73	69		T74	63
valid_sources[0x0d]	53236	1			T72	5		T73	72		T74	66
valid_sources[0x0e]	54224	1			T73	60		T74	72		T77	4
valid_sources[0x0f]	53152	1			T72	2		T73	65		T74	72
valid_sources[0x10]	52450	1			T72	1		T73	58		T74	90
valid_sources[0x11]	52467	1			T72	3		T73	73		T74	69
valid_sources[0x12]	52324	1			T72	2		T73	73		T74	52
valid_sources[0x13]	52930	1			T72	3		T73	65		T74	59
valid_sources[0x14]	52231	1			T72	3		T73	61		T74	70
valid_sources[0x15]	52854	1			T72	3		T73	75		T74	70
valid_sources[0x16]	52528	1			T72	1		T73	72		T74	64
valid_sources[0x17]	53096	1			T72	1		T73	71		T74	52
valid_sources[0x18]	53299	1			T72	5		T73	68		T74	59
valid_sources[0x19]	53390	1			T72	3		T73	73		T74	57
valid_sources[0x1a]	51901	1			T73	66		T74	61		T77	3
valid_sources[0x1b]	52339	1			T73	61		T74	49		T77	3
valid_sources[0x1c]	53756	1			T72	3		T73	54		T74	72
valid_sources[0x1d]	51816	1			T72	4		T73	65		T74	65
valid_sources[0x1e]	52855	1			T72	1		T73	70		T74	69
valid_sources[0x1f]	53452	1			T72	3		T73	72		T74	45
valid_sources[0x20]	52471	1			T73	71		T74	53		T77	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48760

1

T72

3

T73

58

T74

47

values[0x0]

all_enables

biggest_size

364285

1

T72

2

T73

502

T74

432

values[0x1]

all_enables

biggest_size

48179

1

T72

5

T73

59

T74

48