Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528113280	61640841	0	0
DepthKnown_A	528113280	528007085	0	0
RvalidKnown_A	528113280	528007085	0	0
WreadyKnown_A	528113280	528007085	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	61640841	0	0
T4	194917	25424	0	0
T5	146344	14610	0	0
T6	71289	7276	0	0
T16	253587	33471	0	0
T18	126530	136295	0	0
T42	180164	15089	0	0
T60	100192	12150	0	0
T86	72106	7918	0	0
T87	72119	7918	0	0
T88	79830	8182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528113280	47749300	0	0
DepthKnown_A	528113280	528007085	0	0
RvalidKnown_A	528113280	528007085	0	0
WreadyKnown_A	528113280	528007085	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	47749300	0	0
T4	194917	22727	0	0
T5	146344	10508	0	0
T6	71289	5515	0	0
T16	253587	23743	0	0
T18	126530	118546	0	0
T42	180164	11327	0	0
T60	100192	9599	0	0
T86	72106	5544	0	0
T87	72119	5544	0	0
T88	79830	6213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528113280	46266565	0	0
DepthKnown_A	528113280	528007085	0	0
RvalidKnown_A	528113280	528007085	0	0
WreadyKnown_A	528113280	528007085	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	46266565	0	0
T4	194917	5397	0	0
T5	146344	7863	0	0
T6	71289	4342	0	0
T16	253587	16783	0	0
T18	126530	194708	0	0
T42	180164	8785	0	0
T60	100192	6684	0	0
T86	72106	3499	0	0
T87	72119	3499	0	0
T88	79830	4911	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528113280	39958422	0	0
DepthKnown_A	528113280	528007085	0	0
RvalidKnown_A	528113280	528007085	0	0
WreadyKnown_A	528113280	528007085	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	39958422	0	0
T4	194917	5190	0	0
T5	146344	7596	0	0
T6	71289	4227	0	0
T16	253587	16403	0	0
T18	126530	110837	0	0
T42	180164	8540	0	0
T60	100192	6554	0	0
T86	72106	3353	0	0
T87	72119	3353	0	0
T88	79830	4790	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	528007085	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	91845	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	91845	0	0
T4	194917	78	0	0
T5	146344	27	0	0
T6	71289	13	0	0
T16	253587	151	0	0
T18	126530	27	0	0
T42	180164	30	0	0
T60	100192	13	0	0
T86	72106	13	0	0
T87	72119	13	0	0
T88	79830	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	95244	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	95244	0	0
T4	194917	78	0	0
T5	146344	27	0	0
T6	71289	13	0	0
T16	253587	151	0	0
T18	126530	27	0	0
T42	180164	30	0	0
T60	100192	13	0	0
T86	72106	13	0	0
T87	72119	13	0	0
T88	79830	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	50878	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	50878	0	0
T4	194917	77	0	0
T5	146344	25	0	0
T6	71289	12	0	0
T16	253587	95	0	0
T18	126530	0	0	0
T42	180164	28	0	0
T60	100192	12	0	0
T86	72106	12	0	0
T87	72119	12	0	0
T88	79830	14	0	0
T191	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	50878	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	50878	0	0
T4	194917	77	0	0
T5	146344	25	0	0
T6	71289	12	0	0
T16	253587	95	0	0
T18	126530	0	0	0
T42	180164	28	0	0
T60	100192	12	0	0
T86	72106	12	0	0
T87	72119	12	0	0
T88	79830	14	0	0
T191	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	40967	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	40967	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	56	0	0
T18	126530	27	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597673024	44366	0	0
DepthKnown_A	597673024	597555403	0	0
RvalidKnown_A	597673024	597555403	0	0
WreadyKnown_A	597673024	597555403	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	44366	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	56	0	0
T18	126530	27	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597673024	597555403	0	0
T4	194917	194855	0	0
T5	146344	146228	0	0
T6	71289	71234	0	0
T16	253587	253478	0	0
T18	126530	126518	0	0
T42	180164	180048	0	0
T60	100192	100134	0	0
T86	72106	72051	0	0
T87	72119	72061	0	0
T88	79830	79768	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0