Unified Coverage Report :: Module :: tlul_adapter_host

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.09	91.11	75.79			89.44	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex	87.26	90.91	69.23			88.89	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex	90.91	91.30	82.35			90.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.26	90.91	69.23			88.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.90	90.48	72.22			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	94.12	88.24					100.00
u_rsp_chk	93.33	100.00	80.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	91.30	82.35			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.79	95.35	81.82			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	100.00	100.00					100.00
u_rsp_chk	93.33	100.00	80.00				100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.91	91.30

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
TOTAL		23	21	91.30
ALWAYS	70	3	3	100.00
ALWAYS	78	5	5	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	132	4	3	75.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
73	1	1
78	1	1
80	1	1
81	1	1
82	1	1
84	1	1
			MISSING_ELSE
89	1	1
94	1	1
96	1	1
116	1	1
118	1	1
119	1	1
120	1	1
132	1	1
133	1	1
134	1	1
135	0	1
			MISSING_ELSE
141	1	1
145	1	1
149	0	1
153	1	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
87.26	90.91

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	70	3	3	100.00
ALWAYS	78	5	5	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	94	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	132	4	3	75.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
73	1	1
78	1	1
80	1	1
81	1	1
82	1	1
84	1	1
			MISSING_ELSE
89	1	1
94		unreachable
96	1	1
116	1	1
118	1	1
119	1	1
120	1	1
132	1	1
133	1	1
134	1	1
135	0	1
			MISSING_ELSE
141	1	1
145	1	1
149	0	1
153	1	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
87.26	69.23

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T61,T62,T218

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.91	82.35

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Covered	Percent
Conditions	17	14	82.35
Logical	17	14	82.35
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T32,T2,T76
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T16,T61,T62

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.91	90.00

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	94	2	2	100.00
IF	132	3	2	66.67
IF	70	2	2	100.00
IF	80	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Not Covered
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

---

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
87.26	88.89

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	94	1	1	100.00
IF	132	3	2	66.67
IF	70	2	2	100.00
IF	80	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Not Covered
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

---

Assert Coverage for Module : tlul_adapter_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	1056226560	107867276	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056226560	107867276	0	0
T4	389834	30821	0	0
T5	292688	22473	0	0
T6	142578	11618	0	0
T16	507174	50254	0	0
T18	253060	331003	0	0
T42	360328	23874	0	0
T60	200384	18834	0	0
T86	144212	11417	0	0
T87	144238	11417	0	0
T88	159660	13093	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	70	3	3	100.00
ALWAYS	78	5	5	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	94	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	132	4	3	75.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
73	1	1
78	1	1
80	1	1
81	1	1
82	1	1
84	1	1
			MISSING_ELSE
89	1	1
94		unreachable
96	1	1
116	1	1
118	1	1
119	1	1
120	1	1
132	1	1
133	1	1
134	1	1
135	0	1
			MISSING_ELSE
141	1	1
145	1	1
149	0	1
153	1	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T61,T62,T218

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	94	1	1	100.00
IF	132	3	2	66.67
IF	70	2	2	100.00
IF	80	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Not Covered
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	528113280	61640841	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	61640841	0	0
T4	194917	25424	0	0
T5	146344	14610	0	0
T6	71289	7276	0	0
T16	253587	33471	0	0
T18	126530	136295	0	0
T42	180164	15089	0	0
T60	100192	12150	0	0
T86	72106	7918	0	0
T87	72119	7918	0	0
T88	79830	8182	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
TOTAL		23	21	91.30
ALWAYS	70	3	3	100.00
ALWAYS	78	5	5	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	132	4	3	75.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
73	1	1
78	1	1
80	1	1
81	1	1
82	1	1
84	1	1
			MISSING_ELSE
89	1	1
94	1	1
96	1	1
116	1	1
118	1	1
119	1	1
120	1	1
132	1	1
133	1	1
134	1	1
135	0	1
			MISSING_ELSE
141	1	1
145	1	1
149	0	1
153	1	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Covered	Percent
Conditions	17	14	82.35
Logical	17	14	82.35
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T32,T2,T76
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T16,T61,T62

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	94	2	2	100.00
IF	132	3	2	66.67
IF	70	2	2	100.00
IF	80	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Not Covered
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	528113280	46226435	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	46226435	0	0
T4	194917	5397	0	0
T5	146344	7863	0	0
T6	71289	4342	0	0
T16	253587	16783	0	0
T18	126530	194708	0	0
T42	180164	8785	0	0
T60	100192	6684	0	0
T86	72106	3499	0	0
T87	72119	3499	0	0
T88	79830	4911	0	0