Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_i.a_valid	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_o.a_ready	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T706,*T707,*T709	Yes	T706,T707,T709	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T191,*T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T710,T80,T711	Yes	T710,T80,T711	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T269	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T269	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T710,T80,T711	Yes	T710,T80,T711	OUTPUT
cio_rx_i	Yes	Yes	T18,T16,T42	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T53,T17	Yes	T18,T53,T17	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_i.a_valid	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	INPUT
tl_o.a_ready	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_error	Yes	Yes	T72,T77,T79	Yes	T72,T73,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T77,T79	Yes	T72,T73,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T706,*T707,*T709	Yes	T706,T707,T709	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T191,*T53	Yes	T18,T191,T53	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T191,T53	Yes	T18,T191,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T56,T82	Yes	T80,T56,T82	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T56,T82	Yes	T80,T56,T82	OUTPUT
cio_rx_i	Yes	Yes	T18,T16,T42	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T96,T315	Yes	T216,T96,T315	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T96,T315	Yes	T216,T96,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T96,T315	Yes	T216,T96,T315	OUTPUT
intr_tx_done_o	Yes	Yes	T216,T96,T315	Yes	T216,T96,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T96,T315	Yes	T216,T96,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_i.a_valid	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	INPUT
tl_o.a_ready	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
tl_o.d_error	Yes	Yes	T72,T74,T79	Yes	T72,T74,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T74,T79	Yes	T72,T74,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T74,*T77	Yes	T72,T74,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T120,*T214	Yes	T17,T120,T214	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T56,T82	Yes	T80,T56,T82	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T56,T82	Yes	T80,T56,T82	OUTPUT
cio_rx_i	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	INPUT
cio_tx_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T120,T214	Yes	T17,T120,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_i.a_valid	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	INPUT
tl_o.a_ready	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T105,*T148,*T149	Yes	T105,T148,T149	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T710,T80,T712	Yes	T710,T80,T712	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T269	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T269	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T710,T80,T712	Yes	T710,T80,T712	OUTPUT
cio_rx_i	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	INPUT
cio_tx_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
intr_tx_empty_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
intr_rx_watermark_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
intr_tx_done_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
intr_rx_overflow_o	Yes	Yes	T105,T148,T149	Yes	T105,T148,T149	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_i.a_valid	Yes	Yes	T27,T315,T56	Yes	T27,T315,T56	INPUT
tl_o.a_ready	Yes	Yes	T27,T315,T56	Yes	T27,T315,T56	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T27,T315,T29	Yes	T27,T315,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T27,T315,T29	Yes	T27,T315,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T27,*T315,*T29	Yes	T27,T315,T29	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T27,T315,T56	Yes	T27,T315,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T711,T56	Yes	T80,T711,T56	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T711,T56	Yes	T80,T711,T56	OUTPUT
cio_rx_i	Yes	Yes	T27,T29,T332	Yes	T27,T29,T332	INPUT
cio_tx_o	Yes	Yes	T27,T29,T332	Yes	T27,T29,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
intr_tx_empty_o	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
intr_rx_watermark_o	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
intr_tx_done_o	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
intr_rx_overflow_o	Yes	Yes	T27,T315,T29	Yes	T27,T315,T29	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T315,T317,T319	Yes	T315,T317,T319	OUTPUT

*Tests covering at least one bit in the range