Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync	87.50	100.00	50.00			100.00	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T4,T5,T6
EVEN	0	-	Covered	T4,T5,T1
ODD	-	1	Covered	T18,T16,T53
ODD	-	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T4,T5,T6
EVEN	0	-	Covered	T4,T5,T2
ODD	-	1	Covered	T18,T16,T53
ODD	-	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	811968882	4551	0	0
SyncReqAckHoldReq	1058061178	4456	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	811968882	4551	0	0
T1	44504	1	0	0
T2	0	1	0	0
T3	0	3	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	6	0	0
T14	0	3	0	0
T15	0	6	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T33	242857	0	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0
T101	0	3	0	0
T102	41525	0	0	0
T103	50820	0	0	0
T104	91548	0	0	0
T105	274188	0	0	0
T106	65708	0	0	0
T107	64190	0	0	0
T108	123353	0	0	0
T109	69853	0	0	0
T176	15910	3	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058061178	4456	0	0
T1	973	1	0	0
T2	0	1	0	0
T3	0	3	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	6	0	0
T14	0	3	0	0
T15	0	6	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T33	4740	0	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0
T101	0	3	0	0
T102	885	0	0	0
T103	619	0	0	0
T104	1037	0	0	0
T105	2570	0	0	0
T106	826	0	0	0
T107	929	0	0	0
T108	1279	0	0	0
T109	1062	0	0	0
T176	64713	3	0	0