Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T72,T79,T230	Yes	T72,T79,T230	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T61,T62,T218	Yes	T61,T62,T218	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T61,T62,T218	Yes	T61,T62,T218	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T16,T61,T62	Yes	T16,T61,T62	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T16,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T16,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T16,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T16,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T66,T32,T2	Yes	T66,T32,T2	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T66,T32,T75	Yes	T66,T32,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T2,T72,T73	Yes	T2,T72,T73	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T74,T79	Yes	T72,T74,T79	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T74,T79	Yes	T72,T74,T77	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T2,T72,T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T72,T74,T79	Yes	T72,T74,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T2,*T72,*T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T2,T72,T74	Yes	T2,T72,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T236,*T237,*T238	Yes	T236,T237,T238	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T42	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T236,T237,T238	Yes	T236,T237,T238	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T16,T42	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T236,*T237,*T238	Yes	T236,T237,T238	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T16,T42	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T32,T2,T236	Yes	T32,T2,T236	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T18,T53,T164	Yes	T18,T53,T164	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T18,T53,T164	Yes	T18,T53,T164	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T56,T57	Yes	T2,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T2,T56,T57	Yes	T2,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T2,*T72,*T77	Yes	T2,T72,T77	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T72,T79,T78	Yes	T72,T77,T79	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T410,T411,T412	Yes	T410,T411,T412	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T72,T74	Yes	T2,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T2,T410,T411	Yes	T2,T56,T410	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T72,T74,T77	Yes	T72,T77,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T2,T72,*T73	Yes	T2,T72,T74	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T409,*T2,*T97	Yes	T409,T2,T97	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T409,T2,T97	Yes	T409,T2,T97	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T32,T2,T76	Yes	T32,T2,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T16,T218,T358	Yes	T16,T218,T358	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T66,*T32,*T75	Yes	T66,T32,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T26,T193,T194	Yes	T26,T193,T194	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T72,T77,T78	Yes	T72,T77,T79	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T77,T78	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T24,*T32,*T103	Yes	T24,T32,T103	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T24,T32,T103	Yes	T24,T32,T103	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T32,*T103,*T2	Yes	T32,T103,T2	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T32,T103,T2	Yes	T32,T103,T2	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T315,T56,T30	Yes	T315,T56,T30	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	INPUT
tl_usbdev_i.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T223,*T315,*T394	Yes	T223,T315,T394	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T223,T315,T394	Yes	T223,T315,T394	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T77,*T79	Yes	T72,T77,T79	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T16	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T18,T16	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T72,T77,T79	Yes	T72,T74,T77	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T77,T79	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T77,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T16	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T72,*T74,*T77	Yes	T72,T74,T77	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T698,T345,T346	Yes	T698,T345,T346	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_hmac_i.d_error	Yes	Yes	T72,T74,T79	Yes	T72,T74,T79	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
tl_hmac_i.d_sink	Yes	Yes	T72,T74,T79	Yes	T72,T74,T77	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T72,*T74,*T287	Yes	T72,T74,T79	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T72,T74,T79	Yes	T72,T74,T77	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T18,*T53,*T54	Yes	T18,T53,T54	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T265,T442,T32	Yes	T265,T442,T32	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T265,T224,T442	Yes	T265,T224,T442	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T265,T224,T442	Yes	T265,T224,T442	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T265,T442,T32	Yes	T265,T442,T32	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T265,T224,T442	Yes	T265,T224,T442	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T32,*T72,*T77	Yes	T32,T72,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T265,T442,T443	Yes	T265,T442,T443	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T265,T224,T442	Yes	T265,T224,T442	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T265,T224,T442	Yes	T265,T224,T442	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T74,T77	Yes	T72,T77,T287	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T265,T442,T256	Yes	T265,T442,T256	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T265,T442,T256	Yes	T265,T442,T256	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T265,T442,T256	Yes	T265,T442,T32	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T77,T78	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T32,*T72,*T77	Yes	T32,T72,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T265,*T442,*T256	Yes	T265,T442,T32	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T265,T442,T256	Yes	T265,T442,T256	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T60,T86	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T72,*T77,*T79	Yes	T72,T77,T79	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
tl_aes_i.d_error	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
tl_aes_i.d_sink	Yes	Yes	T72,T77,T79	Yes	T72,T77,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T287	Yes	T72,T77,T79	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T60,*T86,*T87	Yes	T60,T86,T87	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T77	Yes	T72,T73,T77	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T115,*T126,*T127	Yes	T53,T54,T115	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T115,T660,T126	Yes	T115,T660,T126	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T72,*T79,*T78	Yes	T72,T79,T78	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T72,T79,T287	Yes	T72,T79,T287	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T72,T74,T79	Yes	T72,T79,T78	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T115,T660,T126	Yes	T115,T660,T126	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T72,T74,T79	Yes	T72,T79,T78	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T72,*T79,*T287	Yes	T72,T79,T78	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T72,T79,T287	Yes	T72,T74,T79	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T115,*T660,*T126	Yes	T115,T660,T126	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T115,T660,T126	Yes	T115,T660,T126	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T115,T660,T126	Yes	T115,T660,T126	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T72,*T77,*T79	Yes	T72,T77,T79	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T115,T660,T126	Yes	T115,T660,T126	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T287	Yes	T72,T77,T79	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T115,*T660,*T126	Yes	T115,T660,T126	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T72,*T77,*T78	Yes	T72,T77,T78	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_edn1_i.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T74,T77	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T74,T77	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T72,*T77,*T79	Yes	T72,T74,T77	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T115,*T126,*T127	Yes	T115,T126,T127	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T115,T126,T127	Yes	T115,T126,T127	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T18,T88	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T72,T78,T287	Yes	T72,T78,T287	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T77,T79	Yes	T72,T74,T77	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T197	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T74,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T88,*T16,*T17	Yes	T88,T16,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T88,T16,T17	Yes	T88,T16,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T32,*T76,*T432	Yes	T32,T76,T432	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_otbn_i.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_otbn_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T32,*T76,*T432	Yes	T32,T76,T432	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T18,*T53,*T54	Yes	T18,T53,T54	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T18,T53,T224	Yes	T18,T53,T224	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T72,*T78,*T287	Yes	T72,T78,T287	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T77,T78	Yes	T72,T77,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T287,T230	Yes	T72,T287,T230	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T103,T67,T116	Yes	T103,T67,T116	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T78,T287	Yes	T72,T77,T287	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T72,*T287,*T230	Yes	T72,T78,T287	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T78,T287	Yes	T72,T287,T230	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T53,*T54,*T172	Yes	T53,T54,T256	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T53,T54,T256	Yes	T53,T54,T256	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T2,*T72,*T73	Yes	T2,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T2,T72,T73	Yes	T2,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T18,T16,T53	Yes	T18,T16,T53	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T18,T16,T53	Yes	T18,T16,T53	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T2,*T72,*T73	Yes	T2,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T72,T73,T78	Yes	T72,T73,T77	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T18,T16	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T32,*T2,*T238	Yes	T32,T2,T238	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T74,T78	Yes	T72,T73,T78	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T32,T2,T174	Yes	T32,T2,T174	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T51,T52	Yes	T18,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T18,T51,T52	Yes	T18,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T72,T77,T79	Yes	T72,T77,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T32,*T2,*T197	Yes	T32,T2,T238	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T77,T79	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T32,*T2,*T118	Yes	T32,T2,T118	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T16	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range