Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3696456	1			T78	61		T79	118		T80	10129
values[2]	749165	1			T78	40		T79	45		T80	1693
values[3]	104511	1			T78	1		T79	1		T80	44
values[4]	55587	1			T80	13		T83	11		T792	10
values[5]	38182	1			T80	13		T792	10		T462	87
values[6]	28704	1			T80	13		T792	10		T462	45
values[7]	22790	1			T80	18		T792	10		T462	8
values[8]	19258	1			T80	25		T792	10		T462	2
values[9]	17676	1			T80	6		T792	10		T462	8
values[10]	16294	1			T80	5		T792	10		T462	6
values[11]	15066	1			T80	3		T792	10		T462	3
values[12]	14155	1			T80	17		T792	10		T462	4
values[13]	13210	1			T80	20		T792	10		T462	2
values[14]	12970	1			T80	15		T792	10		T540	63
values[15]	12618	1			T80	9		T792	10		T540	97
values[16]	12087	1			T80	8		T792	10		T540	90
values[17]	11551	1			T80	18		T792	10		T540	86
values[18]	10852	1			T80	10		T792	10		T540	78
values[19]	10566	1			T80	16		T792	10		T540	70
values[20]	10377	1			T80	15		T792	10		T540	77
values[21]	10164	1			T80	22		T792	10		T540	60
values[22]	9865	1			T80	18		T792	10		T540	68
values[23]	9439	1			T80	9		T792	10		T540	55
values[24]	9210	1			T80	18		T792	10		T540	82
values[25]	8595	1			T80	16		T792	10		T540	57
values[26]	8041	1			T80	9		T792	11		T540	41
values[27]	7981	1			T80	7		T792	10		T540	49
values[28]	7831	1			T80	10		T792	10		T540	46
values[29]	7276	1			T80	11		T792	10		T540	34
values[30]	6825	1			T80	13		T792	10		T540	32
values[31]	6439	1			T80	10		T792	10		T540	24
values[32]	5761	1			T80	11		T792	10		T540	51
values[33]	5617	1			T80	16		T792	10		T540	27
values[34]	5047	1			T80	13		T792	10		T540	26
values[35]	4639	1			T80	10		T792	11		T540	20
values[36]	4346	1			T80	8		T792	10		T540	17
values[37]	4106	1			T80	2		T792	10		T540	24
values[38]	3889	1			T80	3		T792	10		T540	15
values[39]	3661	1			T80	2		T792	10		T540	15
values[40]	3440	1			T80	2		T792	10		T540	15
values[41]	3346	1			T80	3		T792	10		T540	16
values[42]	3273	1			T80	6		T792	10		T540	20
values[43]	3286	1			T80	3		T792	10		T540	21
values[44]	3191	1			T80	3		T792	10		T540	17
values[45]	3081	1			T80	5		T792	10		T540	17
values[46]	3057	1			T80	5		T792	11		T540	20
values[47]	2995	1			T80	7		T792	10		T540	9
values[48]	2915	1			T80	5		T792	10		T540	2
values[49]	2875	1			T80	1		T792	10		T540	7
values[50]	2787	1			T792	10		T540	4		T415	2
values[51]	2700	1			T792	10		T540	10		T415	4
values[52]	2641	1			T792	10		T540	4		T415	3
values[53]	2591	1			T792	10		T540	5		T415	3
values[54]	2658	1			T792	10		T540	5		T415	5
values[55]	2578	1			T792	11		T540	1		T415	3
values[56]	2480	1			T792	10		T540	3		T415	2
values[57]	2498	1			T792	10		T540	2		T415	5
values[58]	2465	1			T792	10		T540	1		T415	3
values[59]	2429	1			T792	10		T540	1		T415	3
values[60]	2473	1			T792	10		T540	2		T415	3
values[61]	2639	1			T792	10		T540	2		T415	3
values[62]	4011	1			T792	10		T540	1		T415	21
values[63]	10543	1			T792	10		T540	1		T415	59
values[64]	227901	1			T792	1918		T540	139		T415	203

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4757047	1			T78	106		T79	120		T80	10882
values[2]	813004	1			T78	26		T79	23		T80	2091
values[3]	83509	1			T78	5		T79	2		T80	56
values[4]	14427	1			T80	10		T83	48		T792	39
values[5]	5230	1			T80	4		T83	12		T792	10
values[6]	3135	1			T80	2		T83	3		T792	2
values[7]	2516	1			T80	2		T792	1		T462	28
values[8]	1981	1			T80	2		T462	15		T540	2
values[9]	1575	1			T80	2		T462	5		T540	1
values[10]	1422	1			T80	2		T462	5		T540	1
values[11]	1375	1			T80	2		T462	9		T540	2
values[12]	1244	1			T80	2		T462	11		T540	1
values[13]	1172	1			T80	2		T462	7		T540	1
values[14]	1218	1			T80	2		T462	11		T540	1
values[15]	1179	1			T80	2		T462	16		T540	2
values[16]	1019	1			T80	2		T462	6		T540	5
values[17]	927	1			T80	2		T462	6		T540	2
values[18]	841	1			T80	2		T462	1		T540	2
values[19]	816	1			T80	3		T462	1		T540	2
values[20]	749	1			T80	2		T462	1		T540	1
values[21]	729	1			T80	2		T462	1		T540	1
values[22]	733	1			T80	2		T462	1		T540	5
values[23]	735	1			T80	2		T462	2		T540	3
values[24]	766	1			T80	1		T462	5		T540	2
values[25]	702	1			T80	1		T462	4		T540	2
values[26]	631	1			T80	2		T462	7		T540	1
values[27]	612	1			T80	2		T462	10		T540	1
values[28]	665	1			T80	2		T462	3		T540	2
values[29]	606	1			T80	2		T462	2		T540	1
values[30]	559	1			T80	2		T462	3		T540	1
values[31]	591	1			T80	2		T462	3		T540	1
values[32]	623	1			T80	2		T462	4		T540	1
values[33]	496	1			T80	2		T462	3		T540	1
values[34]	557	1			T80	2		T462	2		T540	1
values[35]	591	1			T80	2		T462	2		T540	4
values[36]	562	1			T80	3		T462	3		T540	1
values[37]	505	1			T80	2		T462	2		T540	1
values[38]	491	1			T80	2		T462	2		T540	2
values[39]	430	1			T80	2		T462	2		T540	1
values[40]	467	1			T80	2		T462	1		T540	1
values[41]	441	1			T80	1		T462	2		T540	2
values[42]	447	1			T80	1		T462	2		T540	1
values[43]	411	1			T80	2		T462	1		T540	1
values[44]	432	1			T80	3		T462	1		T540	2
values[45]	446	1			T80	3		T462	2		T540	1
values[46]	386	1			T80	2		T462	1		T540	4
values[47]	378	1			T80	2		T462	1		T540	2
values[48]	377	1			T80	2		T462	2		T540	1
values[49]	387	1			T80	2		T462	1		T540	1
values[50]	386	1			T80	2		T462	3		T540	2
values[51]	384	1			T80	2		T462	4		T540	1
values[52]	397	1			T80	2		T462	2		T540	1
values[53]	434	1			T80	2		T462	2		T540	7
values[54]	387	1			T80	2		T462	1		T540	1
values[55]	343	1			T80	2		T462	3		T540	1
values[56]	348	1			T80	2		T462	1		T540	2
values[57]	347	1			T80	2		T540	1		T419	3
values[58]	342	1			T80	2		T540	3		T419	9
values[59]	347	1			T80	2		T540	1		T419	7
values[60]	354	1			T80	2		T540	1		T419	4
values[61]	404	1			T80	2		T540	5		T419	14
values[62]	578	1			T80	2		T540	4		T419	28
values[63]	2045	1			T80	5		T540	1		T419	101
values[64]	25186	1			T80	119		T540	142		T419	190

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	523784	1			T78	1		T79	3		T80	20
values[2]	2712202	1			T78	17		T79	58		T80	10088
values[3]	1158062	1			T78	149		T79	57		T80	1616
values[4]	146492	1			T78	9		T79	2		T80	84
values[5]	74208	1			T80	36		T83	6		T792	10
values[6]	48293	1			T80	44		T792	10		T462	328
values[7]	35420	1			T80	47		T792	10		T462	275
values[8]	28308	1			T80	23		T792	11		T462	218
values[9]	24058	1			T80	20		T792	10		T462	111
values[10]	20944	1			T80	30		T792	10		T462	76
values[11]	18991	1			T80	30		T792	11		T462	55
values[12]	17652	1			T80	38		T792	10		T462	36
values[13]	16581	1			T80	37		T792	10		T462	28
values[14]	15614	1			T80	28		T792	10		T462	24
values[15]	14652	1			T80	17		T792	11		T462	12
values[16]	14347	1			T80	12		T792	11		T462	12
values[17]	13403	1			T80	19		T792	10		T462	10
values[18]	12442	1			T80	17		T792	10		T462	2
values[19]	12111	1			T80	11		T792	10		T462	3
values[20]	12201	1			T80	7		T792	10		T462	2
values[21]	11672	1			T80	12		T792	10		T462	6
values[22]	11357	1			T80	9		T792	10		T462	6
values[23]	10750	1			T80	11		T792	10		T462	10
values[24]	10322	1			T80	10		T792	11		T462	5
values[25]	10155	1			T80	18		T792	10		T462	14
values[26]	9386	1			T80	17		T792	10		T462	11
values[27]	8864	1			T80	16		T792	10		T462	4
values[28]	8534	1			T80	14		T792	10		T462	1
values[29]	7891	1			T80	5		T792	10		T462	1
values[30]	7331	1			T80	8		T792	10		T462	1
values[31]	6758	1			T80	4		T792	10		T462	6
values[32]	6214	1			T80	8		T792	11		T462	2
values[33]	5936	1			T80	13		T792	10		T462	4
values[34]	5561	1			T80	12		T792	10		T462	1
values[35]	5203	1			T80	5		T792	10		T462	2
values[36]	5002	1			T80	5		T792	10		T462	5
values[37]	4748	1			T80	3		T792	10		T462	3
values[38]	4373	1			T80	1		T792	10		T462	4
values[39]	4080	1			T792	10		T462	1		T540	5
values[40]	3782	1			T792	11		T462	1		T540	3
values[41]	3732	1			T792	10		T462	1		T540	1
values[42]	3570	1			T792	10		T462	2		T540	1
values[43]	3557	1			T792	10		T462	1		T415	9
values[44]	3540	1			T792	10		T462	3		T415	4
values[45]	3439	1			T792	10		T462	1		T415	4
values[46]	3272	1			T792	10		T462	5		T415	20
values[47]	3357	1			T792	10		T462	3		T415	11
values[48]	3244	1			T792	11		T462	2		T415	6
values[49]	3259	1			T792	10		T462	7		T415	5
values[50]	3204	1			T792	10		T462	3		T415	7
values[51]	3054	1			T792	10		T462	2		T415	3
values[52]	2996	1			T792	10		T462	2		T415	8
values[53]	2942	1			T792	10		T462	1		T415	2
values[54]	2923	1			T792	10		T462	3		T415	7
values[55]	2916	1			T792	11		T462	4		T415	15
values[56]	2841	1			T792	10		T462	6		T415	5
values[57]	2803	1			T792	10		T462	3		T415	8
values[58]	2689	1			T792	10		T462	4		T415	6
values[59]	2716	1			T792	10		T462	8		T415	7
values[60]	2602	1			T792	10		T462	2		T415	4
values[61]	2774	1			T792	10		T462	2		T415	3
values[62]	3559	1			T792	10		T462	10		T415	5
values[63]	9270	1			T792	10		T462	32		T415	37
values[64]	223422	1			T792	1904		T462	49		T415	86