Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1965409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36508695

1

T4

211073

T5

7303

T6

116114

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26889234	1			T4	190214		T5	4336		T6	101806
values[0x0]	10136609	1			T4	20859		T5	2967		T6	14308
values[0x1]	1448261	1			T4	7		T5	185		T6	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	642409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37831695

1

T4

211080

T5

7488

T6

116125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18054513	1			T4	105540		T5	3744		T6	58063
valid_sources[0x01]	18055221	1			T4	105540		T5	3744		T6	58062
valid_sources[0x02]	38252	1			T71	4		T132	401		T544	10
valid_sources[0x03]	37906	1			T200	1		T132	443		T544	7
valid_sources[0x04]	37667	1			T132	397		T544	10		T381	98
valid_sources[0x05]	38285	1			T132	385		T544	17		T381	75
valid_sources[0x06]	37032	1			T132	363		T544	13		T381	96
valid_sources[0x07]	37830	1			T71	3		T200	4		T132	421
valid_sources[0x08]	37955	1			T200	2		T132	440		T544	12
valid_sources[0x09]	38115	1			T71	1		T200	1		T132	397
valid_sources[0x0a]	40732	1			T132	393		T544	7		T381	89
valid_sources[0x0b]	38212	1			T132	397		T544	6		T381	89
valid_sources[0x0c]	37696	1			T71	2		T132	350		T544	8
valid_sources[0x0d]	39541	1			T200	1		T132	429		T544	11
valid_sources[0x0e]	37931	1			T200	3		T132	375		T544	6
valid_sources[0x0f]	37877	1			T71	1		T132	422		T544	7
valid_sources[0x10]	37821	1			T132	444		T544	13		T381	67
valid_sources[0x11]	37746	1			T132	422		T544	8		T381	66
valid_sources[0x12]	38701	1			T200	6		T132	387		T544	7
valid_sources[0x13]	38743	1			T71	1		T132	375		T544	11
valid_sources[0x14]	38631	1			T132	412		T544	5		T381	127
valid_sources[0x15]	37759	1			T132	433		T544	6		T381	100
valid_sources[0x16]	38218	1			T71	1		T132	409		T544	10
valid_sources[0x17]	37989	1			T132	415		T544	8		T381	97
valid_sources[0x18]	37938	1			T71	5		T132	433		T544	10
valid_sources[0x19]	37142	1			T200	2		T132	445		T544	11
valid_sources[0x1a]	38120	1			T132	384		T544	13		T381	83
valid_sources[0x1b]	39606	1			T200	1		T132	410		T544	8
valid_sources[0x1c]	38173	1			T132	339		T544	7		T381	89
valid_sources[0x1d]	37391	1			T132	390		T544	12		T381	62
valid_sources[0x1e]	37845	1			T71	4		T81	39		T132	374
valid_sources[0x1f]	37861	1			T132	413		T544	15		T381	104
valid_sources[0x20]	38230	1			T132	414		T544	12		T381	94

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26169217

1

T4

190214

T5

4336

T6

101806

values[0x0]

all_enables

biggest_size

10091028

1

T4

20859

T5

2967

T6

14308

values[0x1]

all_enables

biggest_size

248450

1

T58

14

T71

23

T81

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2747551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

433744

1

T78

12

T79

27

T80

54

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1078860	1			T78	26		T79	56		T80	248
values[0x0]	1024065	1			T78	34		T79	56		T80	44
values[0x1]	1078370	1			T78	42		T79	52		T80	242

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2126855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1054440

1

T78

30

T79

62

T80

208

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49760	1			T78	3		T79	1		T80	8
valid_sources[0x01]	49404	1			T78	3		T79	1		T80	15
valid_sources[0x02]	49046	1			T79	4		T80	6		T83	65
valid_sources[0x03]	48755	1			T78	5		T79	3		T80	12
valid_sources[0x04]	49835	1			T78	1		T79	6		T80	8
valid_sources[0x05]	49425	1			T78	3		T79	2		T80	8
valid_sources[0x06]	49868	1			T79	3		T80	8		T82	1
valid_sources[0x07]	50060	1			T78	2		T79	2		T80	7
valid_sources[0x08]	49445	1			T79	1		T80	8		T82	4
valid_sources[0x09]	49794	1			T78	1		T79	6		T80	11
valid_sources[0x0a]	48798	1			T78	4		T79	2		T80	8
valid_sources[0x0b]	49087	1			T78	6		T79	1		T80	8
valid_sources[0x0c]	49286	1			T78	2		T79	4		T80	12
valid_sources[0x0d]	51024	1			T79	6		T80	10		T82	2
valid_sources[0x0e]	49421	1			T78	1		T79	8		T80	4
valid_sources[0x0f]	49965	1			T78	1		T79	1		T80	6
valid_sources[0x10]	50176	1			T78	1		T79	5		T80	9
valid_sources[0x11]	50914	1			T78	1		T79	3		T80	12
valid_sources[0x12]	49505	1			T78	1		T79	5		T80	7
valid_sources[0x13]	49121	1			T78	3		T79	4		T80	9
valid_sources[0x14]	50001	1			T78	1		T79	2		T80	7
valid_sources[0x15]	49949	1			T78	1		T79	2		T80	14
valid_sources[0x16]	49357	1			T79	1		T80	7		T213	4
valid_sources[0x17]	50507	1			T78	1		T79	4		T80	8
valid_sources[0x18]	49109	1			T78	3		T79	4		T80	5
valid_sources[0x19]	49443	1			T79	1		T80	2		T82	2
valid_sources[0x1a]	48445	1			T79	13		T80	11		T82	2
valid_sources[0x1b]	49800	1			T78	1		T79	2		T80	12
valid_sources[0x1c]	49008	1			T78	1		T79	2		T80	15
valid_sources[0x1d]	49654	1			T78	3		T79	4		T80	9
valid_sources[0x1e]	49729	1			T78	3		T79	2		T80	6
valid_sources[0x1f]	48649	1			T80	8		T83	34		T539	10
valid_sources[0x20]	50576	1			T78	2		T79	5		T80	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45997

1

T78

2

T79

3

T80

8

values[0x0]

all_enables

biggest_size

341935

1

T78

9

T79

23

T80

23

values[0x1]

all_enables

biggest_size

45812

1

T78

1

T79

1

T80

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2933219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477149

1

T78

17

T79

18

T80

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1168017	1			T78	50		T79	50		T80	263
values[0x0]	1073930	1			T78	44		T79	44		T80	42
values[0x1]	1168421	1			T78	43		T79	51		T80	272

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2250094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1160274

1

T78

41

T79

45

T80

214

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53259	1			T80	6		T82	1		T83	26
valid_sources[0x01]	53304	1			T78	3		T80	8		T82	3
valid_sources[0x02]	53112	1			T78	4		T79	10		T80	6
valid_sources[0x03]	53159	1			T78	3		T79	9		T80	13
valid_sources[0x04]	53692	1			T78	2		T79	5		T80	6
valid_sources[0x05]	52543	1			T78	7		T79	9		T80	9
valid_sources[0x06]	53249	1			T80	12		T83	43		T463	2
valid_sources[0x07]	53487	1			T80	8		T82	1		T213	3
valid_sources[0x08]	54422	1			T78	11		T80	11		T213	2
valid_sources[0x09]	52867	1			T78	4		T79	3		T80	15
valid_sources[0x0a]	52303	1			T78	4		T80	8		T83	40
valid_sources[0x0b]	52565	1			T78	5		T80	3		T213	5
valid_sources[0x0c]	53277	1			T78	1		T79	4		T80	6
valid_sources[0x0d]	54288	1			T78	6		T79	4		T80	10
valid_sources[0x0e]	52562	1			T78	3		T79	26		T80	8
valid_sources[0x0f]	52166	1			T80	11		T82	1		T83	40
valid_sources[0x10]	52577	1			T78	5		T80	9		T82	1
valid_sources[0x11]	53443	1			T80	3		T213	13		T83	27
valid_sources[0x12]	53254	1			T80	10		T82	1		T83	57
valid_sources[0x13]	54251	1			T78	6		T80	14		T83	58
valid_sources[0x14]	53053	1			T78	1		T80	7		T82	1
valid_sources[0x15]	53567	1			T79	10		T80	8		T82	2
valid_sources[0x16]	53571	1			T80	5		T213	3		T83	52
valid_sources[0x17]	52393	1			T78	1		T80	10		T213	4
valid_sources[0x18]	53610	1			T79	6		T80	12		T82	1
valid_sources[0x19]	52701	1			T80	8		T213	4		T83	16
valid_sources[0x1a]	51975	1			T78	2		T79	3		T80	11
valid_sources[0x1b]	53221	1			T78	4		T80	12		T213	2
valid_sources[0x1c]	52875	1			T80	5		T83	42		T463	2
valid_sources[0x1d]	54082	1			T80	7		T82	1		T213	5
valid_sources[0x1e]	54329	1			T78	2		T80	10		T213	22
valid_sources[0x1f]	51671	1			T79	7		T80	8		T82	1
valid_sources[0x20]	53661	1			T78	3		T80	14		T83	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50134

1

T78

1

T79

2

T80

17

values[0x0]

all_enables

biggest_size

376763

1

T78

12

T79

16

T80

23

values[0x1]

all_enables

biggest_size

50252

1

T78

4

T80

15

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2775889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

438921

1

T78

25

T79

11

T80

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1090762	1			T78	54		T79	41		T80	252
values[0x0]	1034069	1			T78	67		T79	33		T80	57
values[0x1]	1089979	1			T78	55		T79	46		T80	269

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2147402	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1067408

1

T78

50

T79

37

T80

219

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51458	1			T78	4		T80	6		T82	2
valid_sources[0x01]	50677	1			T78	7		T80	6		T82	1
valid_sources[0x02]	50519	1			T78	1		T79	5		T80	15
valid_sources[0x03]	49189	1			T78	2		T79	3		T80	17
valid_sources[0x04]	50132	1			T78	3		T80	4		T213	1
valid_sources[0x05]	49926	1			T78	2		T79	5		T80	2
valid_sources[0x06]	50178	1			T78	1		T80	6		T82	1
valid_sources[0x07]	49691	1			T80	7		T82	2		T83	22
valid_sources[0x08]	50705	1			T78	3		T80	4		T82	1
valid_sources[0x09]	49417	1			T78	2		T80	15		T82	2
valid_sources[0x0a]	49253	1			T78	4		T79	2		T80	12
valid_sources[0x0b]	50135	1			T78	4		T80	6		T83	38
valid_sources[0x0c]	50073	1			T78	2		T80	8		T82	2
valid_sources[0x0d]	50940	1			T78	2		T80	16		T83	35
valid_sources[0x0e]	49297	1			T80	11		T82	2		T213	1
valid_sources[0x0f]	50456	1			T78	3		T80	7		T82	2
valid_sources[0x10]	49914	1			T78	2		T80	15		T82	1
valid_sources[0x11]	50158	1			T78	3		T80	13		T82	2
valid_sources[0x12]	50137	1			T78	1		T80	4		T83	39
valid_sources[0x13]	50065	1			T78	1		T80	5		T82	1
valid_sources[0x14]	50183	1			T78	1		T79	4		T80	11
valid_sources[0x15]	50918	1			T78	5		T80	3		T83	27
valid_sources[0x16]	49797	1			T78	4		T80	5		T82	2
valid_sources[0x17]	50039	1			T78	4		T80	10		T82	1
valid_sources[0x18]	50439	1			T78	2		T80	9		T213	5
valid_sources[0x19]	49732	1			T78	6		T79	2		T80	10
valid_sources[0x1a]	50587	1			T78	2		T80	13		T82	2
valid_sources[0x1b]	48951	1			T79	4		T80	5		T82	1
valid_sources[0x1c]	50708	1			T79	1		T80	7		T82	1
valid_sources[0x1d]	50925	1			T80	13		T213	4		T83	35
valid_sources[0x1e]	50985	1			T78	1		T79	5		T80	12
valid_sources[0x1f]	49529	1			T78	1		T79	1		T80	11
valid_sources[0x20]	50614	1			T78	4		T79	2		T80	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46774

1

T78

1

T79

1

T80

19

values[0x0]

all_enables

biggest_size

345731

1

T78

20

T79

9

T80

22

values[0x1]

all_enables

biggest_size

46416

1

T78

4

T79

1

T80

24