Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
45.52 52.63 38.46 45.45 gen_wkup_detect[1].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
25.56 26.32 23.08 27.27 gen_wkup_detect[3].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
25.56 26.32 23.08 27.27 gen_wkup_detect[6].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.84 63.64 44.44 71.43


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.58 76.47 44.44 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
25.56 26.32 23.08 27.27 gen_wkup_detect[7].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
49.37 57.89 53.85 36.36 gen_wkup_detect[0].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
49.83 57.89 46.15 45.45 gen_wkup_detect[2].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
49.83 57.89 46.15 45.45 gen_wkup_detect[4].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.53 100.00 88.89 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 88.89 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.40 57.89 53.85 45.45 gen_wkup_detect[5].u_pinmux_wkup


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.98 100.00 93.18 94.74 100.00 u_usbdev_aon_wake


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_async.prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Module : prim_filter
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

Branch Coverage for Module : prim_filter
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 70 2 2 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL11763.64
ALWAYS4844100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
ALWAYS5933100.00
CONT_ASSIGN66100.00
CONT_ASSIGN70100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
==> MISSING_ELSE
55 0 1
56 0 1
59 1 1
60 1 1
62 1 1
66 0 1
70 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 70 2 1 50.00
IF 48 3 2 66.67
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T11,T12
01CoveredT2,T11,T13
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT2,T11,T12
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T11,T13

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T2,T11,T12


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT10
01CoveredT10
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT10
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T10


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT14
01CoveredT14
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT14
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT14

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T14


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T3,T7
01CoveredT1,T3,T7
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T3,T7

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 70 2 1 50.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T6


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T1,T3,T7


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT29,T34,T35
01CoveredT29,T34,T35
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT29,T22,T34
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT29,T34,T35

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T29,T22,T34


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 70 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Unreachable


LineNo. Expression -1-: 48 if ((!rst_ni)) -2-: 50 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 59 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%