Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	518196359	60252798	0	0
DepthKnown_A	518196359	518088863	0	0
RvalidKnown_A	518196359	518088863	0	0
WreadyKnown_A	518196359	518088863	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	60252798	0	0
T4	223365	233744	0	0
T5	397789	72243	0	0
T6	129703	143516	0	0
T16	181470	20163	0	0
T17	73882	9605	0	0
T18	157935	21232	0	0
T43	387486	56204	0	0
T44	192772	25122	0	0
T88	100888	12309	0	0
T89	78996	17167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	518196359	46294703	0	0
DepthKnown_A	518196359	518088863	0	0
RvalidKnown_A	518196359	518088863	0	0
WreadyKnown_A	518196359	518088863	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	46294703	0	0
T4	223365	214173	0	0
T5	397789	36779	0	0
T6	129703	124109	0	0
T16	181470	16261	0	0
T17	73882	6455	0	0
T18	157935	16103	0	0
T43	387486	47413	0	0
T44	192772	22426	0	0
T88	100888	9731	0	0
T89	78996	9877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	518196359	42898172	0	0
DepthKnown_A	518196359	518088863	0	0
RvalidKnown_A	518196359	518088863	0	0
WreadyKnown_A	518196359	518088863	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	42898172	0	0
T4	223365	281316	0	0
T5	397789	9138	0	0
T6	129703	188704	0	0
T16	181470	16744	0	0
T17	73882	3973	0	0
T18	157935	9603	0	0
T43	387486	39819	0	0
T44	192772	5162	0	0
T88	100888	8518	0	0
T89	78996	5741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	518196359	36126143	0	0
DepthKnown_A	518196359	518088863	0	0
RvalidKnown_A	518196359	518088863	0	0
WreadyKnown_A	518196359	518088863	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	36126143	0	0
T4	223365	211080	0	0
T5	397789	7488	0	0
T6	129703	116125	0	0
T16	181470	16539	0	0
T17	73882	3827	0	0
T18	157935	9325	0	0
T43	387486	39404	0	0
T44	192772	4958	0	0
T88	100888	8260	0	0
T89	78996	4993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	518088863	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	104964	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	104964	0	0
T4	223365	56	0	0
T5	397789	35	0	0
T6	129703	34	0	0
T16	181470	53	0	0
T17	73882	16	0	0
T18	157935	26	0	0
T43	387486	48	0	0
T44	192772	78	0	0
T88	100888	14	0	0
T89	78996	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	106930	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	106930	0	0
T4	223365	56	0	0
T5	397789	35	0	0
T6	129703	34	0	0
T16	181470	53	0	0
T17	73882	16	0	0
T18	157935	26	0	0
T43	387486	48	0	0
T44	192772	78	0	0
T88	100888	14	0	0
T89	78996	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	54489	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	54489	0	0
T4	223365	5	0	0
T5	397789	35	0	0
T6	129703	5	0	0
T16	181470	52	0	0
T17	73882	13	0	0
T18	157935	23	0	0
T43	387486	41	0	0
T44	192772	77	0	0
T88	100888	13	0	0
T89	78996	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	54489	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	54489	0	0
T4	223365	5	0	0
T5	397789	35	0	0
T6	129703	5	0	0
T16	181470	52	0	0
T17	73882	13	0	0
T18	157935	23	0	0
T43	387486	41	0	0
T44	192772	77	0	0
T88	100888	13	0	0
T89	78996	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	50475	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	50475	0	0
T4	223365	51	0	0
T5	397789	0	0	0
T6	129703	29	0	0
T16	181470	1	0	0
T17	73882	3	0	0
T18	157935	3	0	0
T43	387486	7	0	0
T44	192772	1	0	0
T88	100888	1	0	0
T89	78996	35	0	0
T196	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596913466	52441	0	0
DepthKnown_A	596913466	596793920	0	0
RvalidKnown_A	596913466	596793920	0	0
WreadyKnown_A	596913466	596793920	0	0
gen_passthru_fifo.paramCheckPass	2906	2906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	52441	0	0
T4	223365	51	0	0
T5	397789	0	0	0
T6	129703	29	0	0
T16	181470	1	0	0
T17	73882	3	0	0
T18	157935	3	0	0
T43	387486	7	0	0
T44	192772	1	0	0
T88	100888	1	0	0
T89	78996	35	0	0
T196	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596913466	596793920	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2906	2906	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0