Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T89,T185,T290
0	1	Covered	T89,T185,T290
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T89,T185,T290
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T89,T185,T290

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1036392718	1019305246	0	0
CheckNGreaterZero_A	2032	2032	0	0
GntImpliesReady_A	1036392718	8387	0	0
GntImpliesValid_A	1036392718	8387	0	0
GrantKnown_A	1036392718	1019305246	0	0
IdxKnown_A	1036392718	1019305246	0	0
IndexIsCorrect_A	1036392718	8387	0	0
NoReadyValidNoGrant_A	1036392718	0	0	0
Priority_A	1036392718	8387	0	0
ReadyAndValidImplyGrant_A	1036392718	8387	0	0
ReqAndReadyImplyGrant_A	1036392718	8387	0	0
ReqImpliesValid_A	1036392718	8387	0	0
ValidKnown_A	1036392718	1019305246	0	0
gen_data_port_assertion.DataFlow_A	1036392718	8387	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	1019305246	0	0
T4	446730	446718	0	0
T5	795578	795542	0	0
T6	259406	259396	0	0
T16	362940	362824	0	0
T17	147764	147648	0	0
T18	315870	315768	0	0
T43	774972	774746	0	0
T44	385544	385442	0	0
T88	201776	201660	0	0
T89	157992	157890	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2032	2032	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T43	2	2	0	0
T44	2	2	0	0
T88	2	2	0	0
T89	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	1019305246	0	0
T4	446730	446718	0	0
T5	795578	795542	0	0
T6	259406	259396	0	0
T16	362940	362824	0	0
T17	147764	147648	0	0
T18	315870	315768	0	0
T43	774972	774746	0	0
T44	385544	385442	0	0
T88	201776	201660	0	0
T89	157992	157890	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	1019305246	0	0
T4	446730	446718	0	0
T5	795578	795542	0	0
T6	259406	259396	0	0
T16	362940	362824	0	0
T17	147764	147648	0	0
T18	315870	315768	0	0
T43	774972	774746	0	0
T44	385544	385442	0	0
T88	201776	201660	0	0
T89	157992	157890	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	1019305246	0	0
T4	446730	446718	0	0
T5	795578	795542	0	0
T6	259406	259396	0	0
T16	362940	362824	0	0
T17	147764	147648	0	0
T18	315870	315768	0	0
T43	774972	774746	0	0
T44	385544	385442	0	0
T88	201776	201660	0	0
T89	157992	157890	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036392718	8387	0	0
T19	1619250	0	0	0
T20	109116	0	0	0
T57	266984	0	0	0
T62	295446	0	0	0
T89	157992	2797	0	0
T121	162392	0	0	0
T185	176402	2794	0	0
T196	197278	0	0	0
T253	317298	0	0	0
T290	0	2796	0	0
T299	131802	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T89,T185,T290
0	1	Covered	T89,T185,T290
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T89,T185,T290
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T89,T185,T290

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	518196359	509652623	0	0
CheckNGreaterZero_A	1016	1016	0	0
GntImpliesReady_A	518196359	5196	0	0
GntImpliesValid_A	518196359	5196	0	0
GrantKnown_A	518196359	509652623	0	0
IdxKnown_A	518196359	509652623	0	0
IndexIsCorrect_A	518196359	5196	0	0
NoReadyValidNoGrant_A	518196359	0	0	0
Priority_A	518196359	5196	0	0
ReadyAndValidImplyGrant_A	518196359	5196	0	0
ReqAndReadyImplyGrant_A	518196359	5196	0	0
ReqImpliesValid_A	518196359	5196	0	0
ValidKnown_A	518196359	509652623	0	0
gen_data_port_assertion.DataFlow_A	518196359	5196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	5196	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1732	0	0
T121	81196	0	0	0
T185	88201	1732	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1732	0	0
T299	65901	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T89,T185,T290
0	1	Covered	T89,T185,T290
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T89,T185,T290
1	Covered	T89,T185,T290

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T89,T185,T290
1	0	Covered	T89,T185,T290
1	1	Covered	T89,T185,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T89,T185,T290

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T89,T185,T290
0	Covered	T89,T185,T290

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	518196359	509652623	0	0
CheckNGreaterZero_A	1016	1016	0	0
GntImpliesReady_A	518196359	3191	0	0
GntImpliesValid_A	518196359	3191	0	0
GrantKnown_A	518196359	509652623	0	0
IdxKnown_A	518196359	509652623	0	0
IndexIsCorrect_A	518196359	3191	0	0
NoReadyValidNoGrant_A	518196359	0	0	0
Priority_A	518196359	3191	0	0
ReadyAndValidImplyGrant_A	518196359	3191	0	0
ReqAndReadyImplyGrant_A	518196359	3191	0	0
ReqImpliesValid_A	518196359	3191	0	0
ValidKnown_A	518196359	509652623	0	0
gen_data_port_assertion.DataFlow_A	518196359	3191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	509652623	0	0
T4	223365	223359	0	0
T5	397789	397771	0	0
T6	129703	129698	0	0
T16	181470	181412	0	0
T17	73882	73824	0	0
T18	157935	157884	0	0
T43	387486	387373	0	0
T44	192772	192721	0	0
T88	100888	100830	0	0
T89	78996	78945	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518196359	3191	0	0
T19	809625	0	0	0
T20	54558	0	0	0
T57	133492	0	0	0
T62	147723	0	0	0
T89	78996	1065	0	0
T121	81196	0	0	0
T185	88201	1062	0	0
T196	98639	0	0	0
T253	158649	0	0	0
T290	0	1064	0	0
T299	65901	0	0	0