Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
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Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_chip_env_0.1/chip_env_cov.sv

65 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
aes_fatal_fault 100.00 1 100 1 64 64
aes_recov_ctrl_update_err 100.00 1 100 1 64 64
aon_timer_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_recov_fault 100.00 1 100 1 64 64
csrng_fatal_alert 100.00 1 100 1 64 64
csrng_recov_alert 100.00 1 100 1 64 64
edn0_fatal_alert 100.00 1 100 1 64 64
edn0_recov_alert 100.00 1 100 1 64 64
edn1_fatal_alert 100.00 1 100 1 64 64
edn1_recov_alert 100.00 1 100 1 64 64
entropy_src_fatal_alert 100.00 1 100 1 64 64
entropy_src_recov_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_err 100.00 1 100 1 64 64
flash_ctrl_fatal_prim_flash_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_std_err 100.00 1 100 1 64 64
flash_ctrl_recov_err 100.00 1 100 1 64 64
flash_ctrl_recov_prim_flash_alert 100.00 1 100 1 64 64
gpio_fatal_fault 100.00 1 100 1 64 64
hmac_fatal_fault 100.00 1 100 1 64 64
i2c0_fatal_fault 100.00 1 100 1 64 64
i2c1_fatal_fault 100.00 1 100 1 64 64
i2c2_fatal_fault 100.00 1 100 1 64 64
keymgr_fatal_fault_err 100.00 1 100 1 64 64
keymgr_recov_operation_err 100.00 1 100 1 64 64
kmac_fatal_fault_err 100.00 1 100 1 64 64
kmac_recov_operation_err 100.00 1 100 1 64 64
lc_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
lc_ctrl_fatal_prog_error 100.00 1 100 1 64 64
lc_ctrl_fatal_state_error 100.00 1 100 1 64 64
otbn_fatal 100.00 1 100 1 64 64
otbn_recov 100.00 1 100 1 64 64
otp_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
otp_ctrl_fatal_check_error 100.00 1 100 1 64 64
otp_ctrl_fatal_macro_error 100.00 1 100 1 64 64
otp_ctrl_fatal_prim_otp_alert 100.00 1 100 1 64 64
otp_ctrl_recov_prim_otp_alert 100.00 1 100 1 64 64
pattgen_fatal_fault 100.00 1 100 1 64 64
pinmux_aon_fatal_fault 100.00 1 100 1 64 64
pwm_aon_fatal_fault 100.00 1 100 1 64 64
pwrmgr_aon_fatal_fault 100.00 1 100 1 64 64
rom_ctrl_fatal 100.00 1 100 1 64 64
rstmgr_aon_fatal_cnsty_fault 100.00 1 100 1 64 64
rstmgr_aon_fatal_fault 100.00 1 100 1 64 64
rv_core_ibex_fatal_hw_err 100.00 1 100 1 64 64
rv_core_ibex_fatal_sw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_hw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_sw_err 100.00 1 100 1 64 64
rv_dm_fatal_fault 100.00 1 100 1 64 64
rv_plic_fatal_fault 100.00 1 100 1 64 64
rv_timer_fatal_fault 100.00 1 100 1 64 64
sensor_ctrl_aon_fatal_alert 100.00 1 100 1 64 64
sensor_ctrl_aon_recov_alert 100.00 1 100 1 64 64
spi_device_fatal_fault 100.00 1 100 1 64 64
spi_host0_fatal_fault 100.00 1 100 1 64 64
spi_host1_fatal_fault 100.00 1 100 1 64 64
sram_ctrl_main_fatal_error 100.00 1 100 1 64 64
sram_ctrl_ret_aon_fatal_error 100.00 1 100 1 64 64
sysrst_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
uart0_fatal_fault 100.00 1 100 1 64 64
uart1_fatal_fault 100.00 1 100 1 64 64
uart2_fatal_fault 100.00 1 100 1 64 64
uart3_fatal_fault 100.00 1 100 1 64 64
usbdev_fatal_fault 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance adc_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_recov_ctrl_update_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_recov_ctrl_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_recov_ctrl_update_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aon_timer_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aon_timer_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_recov_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_recov_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_recov_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_std_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_std_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_std_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : gpio_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance gpio_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : hmac_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance hmac_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_prog_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_prog_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_prog_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_state_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_state_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_state_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_recov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_recov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_recov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_check_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_check_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_check_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_macro_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_macro_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_macro_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_recov_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_recov_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_recov_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pattgen_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pattgen_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pinmux_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pinmux_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwm_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwm_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwrmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwrmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rom_ctrl_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rom_ctrl_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_cnsty_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_cnsty_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_cnsty_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_dm_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_dm_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_plic_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_plic_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_timer_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_timer_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_device_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_device_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_main_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_main_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_ret_aon_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_ret_aon_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sysrst_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sysrst_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart3_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart3_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : usbdev_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance usbdev_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5507 1 T57 1 T102 808 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 115621 1 T5 590 T6 67 T16 586


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 172 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3849 1 T174 810 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2515 1 T57 1 T58 1 T664 511


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 798 1 T57 1 T58 1 T666 103


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2991 1 T57 1 T333 1734 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 168 1 T57 1 T360 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5871 1 T57 1 T612 1141 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 173 1 T57 1 T360 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2423 1 T57 1 T58 1 T648 1102


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 152 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 9328 1 T57 1 T58 1 T345 1717


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 188 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8498 1 T64 1712 T57 1 T103 309


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 12212 1 T57 1 T58 1 T670 1120


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3616 1 T57 1 T58 1 T242 1730


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 387 1 T113 2 T57 1 T401 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 152 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2314 1 T57 1 T58 1 T661 521


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 11539 1 T57 1 T58 1 T671 1124


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2351 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4261 1 T5 814 T57 1 T364 810


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2843 1 T57 1 T58 1 T662 812


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6478 1 T57 1 T58 1 T672 1729


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 145 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 120067 1 T5 590 T6 67 T16 586


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 156 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 983 1 T57 1 T58 1 T650 820


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1901 1 T57 1 T58 1 T169 572


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4223 1 T57 1 T58 1 T165 805


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1390754 1 T5 590 T6 67 T16 586


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 171 1 T57 1 T122 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1533 1 T16 809 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 52074 1 T5 280 T6 33 T16 275


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 976 1 T57 1 T58 1 T165 805


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5501 1 T57 1 T58 1 T663 819


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 181 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5309 1 T95 515 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1524 1 T61 517 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 697 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7447 1 T15 1 T119 963 T617 497


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 13227 1 T57 1 T58 1 T342 1726


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3091 1 T57 1 T58 1 T665 808


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 994 1 T57 1 T58 1 T2 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 32783 1 T114 272 T115 254 T57 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2580 1 T57 1 T58 1 T2 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 120 1 T57 1 T58 1 T2 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 247 1 T55 1 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5713 1 T2 1 T654 1064 T655 1059


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4685 1 T57 1 T58 1 T303 1734


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5180 1 T57 1 T58 1 T667 519


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4550 1 T57 1 T335 810 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 12430 1 T120 1 T57 1 T1 1189


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4180 1 T158 511 T57 1 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6193 1 T57 1 T58 1 T673 1074


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1474 1 T57 1 T58 1 T657 1303


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1876 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 199 1 T57 1 T58 1 T204 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3878 1 T57 1 T58 1 T668 529


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2868 1 T57 1 T644 533 T58 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1007 1 T57 1 T58 1 T658 821


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2813 1 T57 1 T58 1 T59 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1731 1 T57 1 T58 1 T669 518


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3584 1 T57 1 T334 1303 T58 1

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