Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3530243	1			T77	5		T78	870		T79	89
values[2]	705015	1			T77	5		T78	78		T79	25
values[3]	99911	1			T77	5		T79	20		T123	187
values[4]	53408	1			T77	5		T79	2		T123	79
values[5]	36537	1			T77	5		T123	57		T83	195
values[6]	27269	1			T77	5		T123	26		T83	143
values[7]	22555	1			T77	5		T123	6		T83	136
values[8]	19396	1			T77	5		T123	10		T83	89
values[9]	17318	1			T77	5		T123	12		T83	59
values[10]	15999	1			T77	6		T123	14		T83	70
values[11]	14922	1			T77	5		T123	8		T83	109
values[12]	14169	1			T77	5		T123	12		T83	114
values[13]	13267	1			T77	5		T123	11		T83	94
values[14]	12802	1			T77	5		T123	11		T83	61
values[15]	12329	1			T77	5		T123	11		T83	34
values[16]	11988	1			T77	5		T123	8		T83	33
values[17]	11519	1			T77	5		T123	21		T83	16
values[18]	10849	1			T77	5		T123	15		T83	17
values[19]	10643	1			T77	5		T123	10		T83	21
values[20]	10117	1			T77	5		T123	6		T83	9
values[21]	9879	1			T77	5		T123	5		T83	14
values[22]	9450	1			T77	5		T123	9		T83	13
values[23]	9222	1			T77	5		T123	8		T83	19
values[24]	8869	1			T77	5		T123	8		T83	13
values[25]	8671	1			T77	5		T123	6		T83	17
values[26]	8056	1			T77	5		T123	9		T83	24
values[27]	7692	1			T77	5		T123	8		T83	18
values[28]	7155	1			T77	5		T123	11		T83	17
values[29]	6785	1			T77	5		T123	15		T83	12
values[30]	6362	1			T77	5		T123	5		T83	17
values[31]	5927	1			T77	5		T123	7		T83	12
values[32]	5561	1			T77	5		T123	3		T83	15
values[33]	5152	1			T77	5		T123	7		T83	17
values[34]	4604	1			T77	5		T123	5		T83	16
values[35]	4414	1			T77	5		T123	5		T83	16
values[36]	4121	1			T77	5		T123	6		T83	16
values[37]	3957	1			T77	5		T123	3		T83	16
values[38]	3804	1			T77	5		T123	5		T83	32
values[39]	3597	1			T77	5		T123	8		T83	28
values[40]	3439	1			T77	6		T123	6		T83	14
values[41]	3351	1			T77	5		T123	6		T83	8
values[42]	3290	1			T77	5		T123	3		T83	15
values[43]	3227	1			T77	5		T123	6		T83	23
values[44]	3088	1			T77	5		T123	5		T83	21
values[45]	3067	1			T77	5		T123	6		T83	21
values[46]	2988	1			T77	5		T123	6		T83	16
values[47]	3004	1			T77	5		T123	5		T83	20
values[48]	2959	1			T77	5		T123	6		T83	14
values[49]	2873	1			T77	5		T123	5		T83	15
values[50]	2837	1			T77	5		T123	3		T83	14
values[51]	2824	1			T77	5		T123	8		T83	15
values[52]	2686	1			T77	5		T123	7		T83	11
values[53]	2733	1			T77	5		T123	4		T83	18
values[54]	2598	1			T77	5		T123	6		T83	20
values[55]	2573	1			T77	5		T123	8		T83	12
values[56]	2568	1			T77	5		T123	8		T83	27
values[57]	2527	1			T77	5		T123	10		T83	28
values[58]	2402	1			T77	5		T123	5		T83	18
values[59]	2428	1			T77	5		T123	5		T83	17
values[60]	2468	1			T77	5		T123	4		T83	19
values[61]	2667	1			T77	5		T123	8		T83	18
values[62]	3825	1			T77	6		T123	13		T83	55
values[63]	10298	1			T77	6		T123	37		T83	209
values[64]	235140	1			T77	982		T123	172		T83	423

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4546557	1			T77	884		T78	819		T79	68
values[2]	773183	1			T77	216		T78	64		T79	27
values[3]	81973	1			T77	62		T79	11		T123	28
values[4]	13919	1			T77	18		T79	9		T123	3
values[5]	5008	1			T77	3		T79	2		T83	6
values[6]	2956	1			T83	14		T502	1		T394	2
values[7]	2354	1			T83	12		T393	2		T389	5
values[8]	2009	1			T83	5		T393	2		T389	1
values[9]	1709	1			T83	6		T393	2		T389	1
values[10]	1559	1			T83	8		T393	3		T389	1
values[11]	1599	1			T83	8		T393	2		T389	5
values[12]	1476	1			T83	13		T393	2		T389	2
values[13]	1316	1			T83	10		T393	2		T389	1
values[14]	1187	1			T83	6		T393	1		T389	1
values[15]	998	1			T83	5		T393	1		T389	4
values[16]	938	1			T83	4		T393	2		T389	1
values[17]	917	1			T83	10		T393	3		T389	2
values[18]	928	1			T83	14		T393	2		T389	1
values[19]	900	1			T83	17		T393	2		T389	1
values[20]	876	1			T83	12		T393	5		T389	1
values[21]	769	1			T83	4		T393	2		T389	2
values[22]	803	1			T83	7		T393	2		T389	1
values[23]	763	1			T83	6		T393	1		T389	1
values[24]	643	1			T83	4		T393	1		T389	3
values[25]	692	1			T83	6		T393	2		T389	2
values[26]	656	1			T83	13		T393	5		T389	4
values[27]	628	1			T83	21		T393	2		T389	3
values[28]	601	1			T83	7		T393	2		T389	3
values[29]	619	1			T83	3		T393	2		T389	4
values[30]	609	1			T83	5		T393	2		T389	1
values[31]	600	1			T83	5		T393	2		T389	2
values[32]	576	1			T83	9		T393	2		T389	2
values[33]	560	1			T83	10		T393	2		T389	5
values[34]	524	1			T83	7		T393	2		T389	2
values[35]	493	1			T83	4		T393	2		T389	1
values[36]	506	1			T83	8		T393	2		T389	2
values[37]	515	1			T83	2		T393	2		T389	1
values[38]	437	1			T83	3		T393	2		T389	1
values[39]	458	1			T83	4		T393	2		T389	1
values[40]	456	1			T83	4		T393	2		T389	1
values[41]	479	1			T83	4		T393	1		T389	1
values[42]	429	1			T83	6		T393	3		T389	1
values[43]	416	1			T83	7		T393	3		T389	2
values[44]	383	1			T83	2		T393	1		T389	4
values[45]	349	1			T83	5		T393	1		T389	1
values[46]	369	1			T83	6		T393	3		T389	1
values[47]	366	1			T83	6		T393	3		T389	2
values[48]	371	1			T83	10		T393	2		T389	1
values[49]	373	1			T83	3		T393	2		T389	2
values[50]	406	1			T83	3		T393	2		T389	1
values[51]	353	1			T83	1		T393	2		T389	3
values[52]	328	1			T83	1		T393	2		T389	1
values[53]	367	1			T83	5		T393	2		T389	1
values[54]	337	1			T83	1		T393	2		T389	1
values[55]	332	1			T83	5		T393	2		T389	1
values[56]	335	1			T83	1		T393	2		T389	2
values[57]	339	1			T83	1		T393	2		T389	2
values[58]	301	1			T83	4		T393	2		T389	1
values[59]	300	1			T83	2		T393	2		T389	1
values[60]	319	1			T83	2		T393	2		T389	2
values[61]	319	1			T393	2		T389	3		T782	4
values[62]	514	1			T393	2		T389	2		T782	3
values[63]	1942	1			T393	5		T389	7		T782	15
values[64]	24385	1			T393	115		T389	111		T782	255

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	559089	1			T77	5		T78	6		T79	1
values[2]	2443043	1			T77	5		T78	759		T79	65
values[3]	1167529	1			T77	5		T78	67		T79	23
values[4]	142267	1			T77	5		T79	2		T123	184
values[5]	72710	1			T77	5		T123	81		T83	695
values[6]	47478	1			T77	5		T123	52		T83	411
values[7]	34295	1			T77	5		T123	17		T83	252
values[8]	27336	1			T77	5		T123	13		T83	154
values[9]	23080	1			T77	5		T123	12		T83	138
values[10]	20497	1			T77	5		T123	11		T83	139
values[11]	18838	1			T77	5		T123	15		T83	159
values[12]	17272	1			T77	5		T123	15		T83	109
values[13]	16184	1			T77	5		T123	18		T83	64
values[14]	15052	1			T77	5		T123	14		T83	74
values[15]	14469	1			T77	5		T123	21		T83	30
values[16]	13886	1			T77	5		T123	11		T83	23
values[17]	13672	1			T77	5		T123	8		T83	23
values[18]	13036	1			T77	5		T123	10		T83	42
values[19]	12833	1			T77	5		T123	10		T83	26
values[20]	12319	1			T77	5		T123	14		T83	24
values[21]	11666	1			T77	5		T123	18		T83	33
values[22]	11184	1			T77	5		T123	12		T83	36
values[23]	10722	1			T77	5		T123	10		T83	21
values[24]	9877	1			T77	5		T123	17		T83	28
values[25]	9345	1			T77	5		T123	15		T83	24
values[26]	8937	1			T77	5		T123	14		T83	23
values[27]	8694	1			T77	5		T123	19		T83	33
values[28]	8500	1			T77	5		T123	10		T83	24
values[29]	7820	1			T77	5		T123	8		T83	16
values[30]	7048	1			T77	5		T123	10		T83	22
values[31]	6613	1			T77	5		T123	14		T83	25
values[32]	6205	1			T77	5		T123	15		T83	18
values[33]	5815	1			T77	5		T123	14		T83	26
values[34]	5424	1			T77	5		T123	7		T83	31
values[35]	5116	1			T77	5		T123	3		T83	37
values[36]	4718	1			T77	5		T123	5		T83	39
values[37]	4350	1			T77	5		T123	13		T83	51
values[38]	4115	1			T77	5		T123	20		T83	34
values[39]	3940	1			T77	5		T123	30		T83	36
values[40]	3762	1			T77	5		T123	15		T83	26
values[41]	3686	1			T77	5		T123	12		T83	23
values[42]	3638	1			T77	5		T123	9		T83	31
values[43]	3412	1			T77	5		T123	7		T83	16
values[44]	3279	1			T77	5		T123	8		T83	17
values[45]	3369	1			T77	5		T123	4		T83	30
values[46]	3405	1			T77	5		T123	3		T83	24
values[47]	3308	1			T77	5		T123	7		T83	18
values[48]	3154	1			T77	5		T123	11		T83	11
values[49]	3158	1			T77	5		T123	7		T83	27
values[50]	3117	1			T77	5		T123	12		T83	32
values[51]	3031	1			T77	5		T123	14		T83	13
values[52]	2981	1			T77	5		T123	12		T83	17
values[53]	2997	1			T77	5		T123	10		T83	16
values[54]	2953	1			T77	5		T123	4		T83	23
values[55]	2987	1			T77	5		T123	3		T83	16
values[56]	2848	1			T77	5		T123	3		T83	11
values[57]	2815	1			T77	5		T123	4		T83	14
values[58]	2715	1			T77	5		T123	2		T83	28
values[59]	2646	1			T77	5		T123	4		T83	22
values[60]	2541	1			T77	5		T123	4		T83	16
values[61]	2538	1			T77	5		T123	2		T83	11
values[62]	3392	1			T77	5		T123	6		T83	36
values[63]	8695	1			T77	7		T123	25		T83	181
values[64]	228278	1			T77	940		T123	73		T83	409