Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1632207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34906023

1

T4

6747

T5

17521

T15

37973

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25469272	1			T4	3007		T5	8459		T15	28459
values[0x0]	9741188	1			T4	3740		T5	9062		T15	9514
values[0x1]	1327770	1			T4	417		T5	1523		T15	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	461368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36076862

1

T4

7164

T5

19044

T15

38082

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17334749	1			T4	3582		T5	9523		T15	19041
valid_sources[0x01]	17334406	1			T4	3582		T5	9521		T15	19041
valid_sources[0x02]	30511	1			T2	1		T81	1		T411	37
valid_sources[0x03]	29771	1			T411	30		T140	820		T613	7
valid_sources[0x04]	30347	1			T2	1		T81	1		T411	32
valid_sources[0x05]	29047	1			T81	1		T411	21		T140	749
valid_sources[0x06]	30023	1			T81	1		T206	1		T411	36
valid_sources[0x07]	35231	1			T2	1		T81	2		T206	2
valid_sources[0x08]	29381	1			T81	1		T206	1		T411	36
valid_sources[0x09]	31843	1			T2	2		T411	44		T140	906
valid_sources[0x0a]	30689	1			T206	1		T411	34		T140	809
valid_sources[0x0b]	29674	1			T206	3		T411	36		T140	762
valid_sources[0x0c]	33687	1			T2	1		T206	1		T411	29
valid_sources[0x0d]	30307	1			T18	1		T81	1		T206	1
valid_sources[0x0e]	28705	1			T18	2		T81	1		T206	1
valid_sources[0x0f]	29639	1			T2	3		T411	34		T140	757
valid_sources[0x10]	31276	1			T411	38		T140	790		T613	1
valid_sources[0x11]	28923	1			T18	3		T2	1		T81	1
valid_sources[0x12]	29911	1			T2	1		T81	1		T411	24
valid_sources[0x13]	30458	1			T18	5		T2	1		T81	1
valid_sources[0x14]	29423	1			T2	1		T81	1		T206	2
valid_sources[0x15]	30171	1			T2	1		T81	1		T205	4
valid_sources[0x16]	29417	1			T18	2		T2	1		T206	1
valid_sources[0x17]	29582	1			T2	2		T81	2		T206	1
valid_sources[0x18]	29760	1			T2	1		T81	1		T206	1
valid_sources[0x19]	28615	1			T206	1		T411	36		T140	803
valid_sources[0x1a]	29806	1			T81	1		T411	28		T140	826
valid_sources[0x1b]	29437	1			T205	30		T411	34		T140	814
valid_sources[0x1c]	29956	1			T18	6		T206	2		T411	38
valid_sources[0x1d]	30259	1			T81	1		T204	39		T205	5
valid_sources[0x1e]	29989	1			T411	30		T140	776		T613	2
valid_sources[0x1f]	29341	1			T81	1		T206	2		T411	25
valid_sources[0x20]	29871	1			T18	2		T206	1		T411	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24974694

1

T4

3007

T5

8459

T15

28459

values[0x0]

all_enables

biggest_size

9702249

1

T4

3740

T5

9062

T15

9514

values[0x1]

all_enables

biggest_size

229080

1

T18

15

T2

15

T81

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2813949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445382

1

T77

187

T78

2

T79

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1102711	1			T77	410		T78	10		T79	45
values[0x0]	1053405	1			T77	447		T78	3		T79	53
values[0x1]	1103215	1			T77	444		T78	20		T79	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2177520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1081811

1

T77

428

T78

14

T79

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50190	1			T77	27		T79	5		T123	21
valid_sources[0x01]	51305	1			T77	21		T79	7		T123	8
valid_sources[0x02]	50466	1			T77	19		T79	2		T123	11
valid_sources[0x03]	50983	1			T77	26		T79	2		T123	17
valid_sources[0x04]	51000	1			T77	19		T79	1		T123	20
valid_sources[0x05]	51232	1			T77	17		T79	1		T123	14
valid_sources[0x06]	49801	1			T77	17		T79	2		T123	20
valid_sources[0x07]	50974	1			T77	16		T79	1		T123	15
valid_sources[0x08]	50463	1			T77	17		T79	4		T123	13
valid_sources[0x09]	51521	1			T77	19		T79	1		T123	16
valid_sources[0x0a]	51032	1			T77	21		T78	1		T123	19
valid_sources[0x0b]	51180	1			T77	22		T78	1		T79	1
valid_sources[0x0c]	52016	1			T77	20		T79	2		T123	23
valid_sources[0x0d]	51100	1			T77	20		T79	4		T123	18
valid_sources[0x0e]	50630	1			T77	18		T79	2		T123	31
valid_sources[0x0f]	52484	1			T77	24		T78	1		T79	1
valid_sources[0x10]	50622	1			T77	21		T123	19		T82	89
valid_sources[0x11]	49662	1			T77	23		T79	1		T123	11
valid_sources[0x12]	50296	1			T77	20		T79	1		T123	9
valid_sources[0x13]	51457	1			T77	21		T78	2		T79	1
valid_sources[0x14]	50844	1			T77	15		T78	2		T123	12
valid_sources[0x15]	51330	1			T77	19		T79	3		T123	12
valid_sources[0x16]	51693	1			T77	19		T78	1		T79	1
valid_sources[0x17]	51459	1			T77	18		T123	8		T82	128
valid_sources[0x18]	50224	1			T77	26		T123	27		T82	52
valid_sources[0x19]	52849	1			T77	23		T79	7		T123	9
valid_sources[0x1a]	51272	1			T77	18		T123	14		T82	128
valid_sources[0x1b]	51092	1			T77	17		T79	1		T123	28
valid_sources[0x1c]	51043	1			T77	16		T79	3		T123	42
valid_sources[0x1d]	51062	1			T77	22		T78	1		T79	1
valid_sources[0x1e]	50836	1			T77	24		T79	4		T123	19
valid_sources[0x1f]	50307	1			T77	25		T78	1		T79	1
valid_sources[0x20]	48977	1			T77	22		T79	5		T123	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46449

1

T77

15

T79

1

T123

15

values[0x0]

all_enables

biggest_size

352075

1

T77

155

T78

2

T79

17

values[0x1]

all_enables

biggest_size

46858

1

T77

17

T79

2

T123

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2998454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

488499

1

T77

172

T78

4

T79

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1194177	1			T77	374		T78	16		T79	28
values[0x0]	1101997	1			T77	419		T78	6		T79	53
values[0x1]	1190779	1			T77	390		T78	10		T79	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2302569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1184384

1

T77

401

T78

9

T79

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54866	1			T77	8		T79	2		T123	13
valid_sources[0x01]	55119	1			T77	12		T123	21		T82	58
valid_sources[0x02]	53938	1			T77	5		T123	34		T82	73
valid_sources[0x03]	54470	1			T77	19		T79	2		T123	22
valid_sources[0x04]	55071	1			T77	46		T123	15		T82	89
valid_sources[0x05]	54285	1			T77	5		T79	1		T123	24
valid_sources[0x06]	54079	1			T77	37		T79	2		T123	17
valid_sources[0x07]	54012	1			T77	4		T123	28		T82	16
valid_sources[0x08]	54973	1			T77	3		T123	19		T82	80
valid_sources[0x09]	54779	1			T77	18		T79	1		T123	10
valid_sources[0x0a]	54525	1			T77	40		T79	2		T123	16
valid_sources[0x0b]	54009	1			T77	32		T78	2		T79	1
valid_sources[0x0c]	54362	1			T77	37		T123	8		T82	78
valid_sources[0x0d]	54943	1			T77	7		T79	9		T123	21
valid_sources[0x0e]	54006	1			T78	2		T123	19		T82	111
valid_sources[0x0f]	54692	1			T77	8		T78	1		T79	7
valid_sources[0x10]	53806	1			T77	20		T78	2		T79	2
valid_sources[0x11]	55397	1			T77	5		T123	12		T82	108
valid_sources[0x12]	55276	1			T77	20		T78	1		T79	3
valid_sources[0x13]	55102	1			T77	14		T79	1		T123	17
valid_sources[0x14]	55019	1			T77	34		T78	1		T79	2
valid_sources[0x15]	54966	1			T77	21		T123	22		T82	131
valid_sources[0x16]	55465	1			T77	18		T79	1		T123	15
valid_sources[0x17]	54220	1			T77	11		T78	3		T123	15
valid_sources[0x18]	53500	1			T77	20		T79	3		T123	29
valid_sources[0x19]	55218	1			T77	15		T123	28		T82	55
valid_sources[0x1a]	55804	1			T77	29		T123	13		T82	54
valid_sources[0x1b]	54622	1			T77	15		T79	3		T123	20
valid_sources[0x1c]	53944	1			T77	3		T123	24		T82	25
valid_sources[0x1d]	53925	1			T77	19		T78	1		T123	7
valid_sources[0x1e]	54740	1			T77	23		T78	1		T79	2
valid_sources[0x1f]	53966	1			T77	9		T78	2		T123	14
valid_sources[0x20]	54348	1			T77	29		T78	1		T123	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51066

1

T77

18

T79

2

T123

15

values[0x0]

all_enables

biggest_size

386756

1

T77

143

T78

2

T79

18

values[0x1]

all_enables

biggest_size

50677

1

T77

11

T78

2

T123

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2834322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

448389

1

T77

174

T78

3

T79

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1110748	1			T77	429		T78	18		T79	30
values[0x0]	1062335	1			T77	438		T78	5		T79	32
values[0x1]	1109628	1			T77	390		T78	26		T79	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2195837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1086874

1

T77

402

T78

16

T79

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51753	1			T77	29		T79	3		T123	14
valid_sources[0x01]	51998	1			T77	16		T79	1		T123	15
valid_sources[0x02]	51289	1			T77	19		T79	2		T123	23
valid_sources[0x03]	51875	1			T77	13		T78	2		T79	2
valid_sources[0x04]	51239	1			T77	18		T79	1		T123	21
valid_sources[0x05]	51516	1			T77	16		T123	19		T82	124
valid_sources[0x06]	50922	1			T77	24		T79	6		T123	20
valid_sources[0x07]	50959	1			T77	19		T79	2		T123	25
valid_sources[0x08]	51188	1			T77	22		T79	2		T123	22
valid_sources[0x09]	50887	1			T77	14		T79	1		T123	19
valid_sources[0x0a]	51282	1			T77	15		T79	3		T123	26
valid_sources[0x0b]	51682	1			T77	19		T79	2		T123	17
valid_sources[0x0c]	51905	1			T77	19		T123	17		T82	81
valid_sources[0x0d]	51120	1			T77	19		T79	1		T123	24
valid_sources[0x0e]	50398	1			T77	17		T78	1		T79	1
valid_sources[0x0f]	51608	1			T77	17		T123	15		T82	70
valid_sources[0x10]	50793	1			T77	17		T78	4		T123	12
valid_sources[0x11]	50737	1			T77	22		T78	1		T79	1
valid_sources[0x12]	50943	1			T77	19		T78	2		T79	1
valid_sources[0x13]	51105	1			T77	12		T123	14		T82	90
valid_sources[0x14]	50821	1			T77	25		T79	3		T123	13
valid_sources[0x15]	52078	1			T77	25		T79	3		T123	15
valid_sources[0x16]	51823	1			T77	18		T123	17		T82	51
valid_sources[0x17]	51957	1			T77	15		T78	2		T79	1
valid_sources[0x18]	50743	1			T77	20		T79	1		T123	17
valid_sources[0x19]	51883	1			T77	23		T78	1		T123	13
valid_sources[0x1a]	51725	1			T77	19		T79	3		T123	21
valid_sources[0x1b]	51073	1			T77	23		T78	1		T79	1
valid_sources[0x1c]	51027	1			T77	20		T79	1		T123	20
valid_sources[0x1d]	51643	1			T77	14		T79	1		T123	15
valid_sources[0x1e]	51320	1			T77	23		T79	1		T123	20
valid_sources[0x1f]	50974	1			T77	16		T79	2		T123	24
valid_sources[0x20]	51971	1			T77	22		T79	3		T123	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46846

1

T77

17

T78

1

T79

1

values[0x0]

all_enables

biggest_size

354534

1

T77

143

T78

2

T79

9

values[0x1]

all_enables

biggest_size

47009

1

T77

14

T79

2

T123

16