Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg
Group Instance : adc_ctrl_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance adc_ctrl_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance adc_ctrl_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : aes
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance aes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance aes
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : alert_handler
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance alert_handler
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance alert_handler
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : aon_timer_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance aon_timer_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance aon_timer_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : ast
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance ast
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance ast
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : clkmgr_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance clkmgr_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance clkmgr_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : csrng
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance csrng
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance csrng
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : edn0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance edn0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance edn0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : edn1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance edn1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance edn1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : entropy_src
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance entropy_src
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance entropy_src
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : flash_ctrl__core
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance flash_ctrl__core
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance flash_ctrl__core
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : flash_ctrl__mem
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance flash_ctrl__mem
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance flash_ctrl__mem
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : flash_ctrl__prim
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance flash_ctrl__prim
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance flash_ctrl__prim
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : gpio
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance gpio
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance gpio
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : hmac
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance hmac
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance hmac
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : i2c0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance i2c0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance i2c0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : i2c1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance i2c1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance i2c1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : i2c2
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance i2c2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance i2c2
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : keymgr
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance keymgr
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : kmac
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance kmac
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance kmac
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : lc_ctrl
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance lc_ctrl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance lc_ctrl
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : otbn
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance otbn
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance otbn
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : otp_ctrl__core
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance otp_ctrl__core
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance otp_ctrl__core
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : otp_ctrl__prim
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance otp_ctrl__prim
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance otp_ctrl__prim
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : pattgen
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance pattgen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance pattgen
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : pinmux_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance pinmux_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance pinmux_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : pwm_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance pwm_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance pwm_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : pwrmgr_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance pwrmgr_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance pwrmgr_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rom_ctrl__regs
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rom_ctrl__regs
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rom_ctrl__regs
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rom_ctrl__rom
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rom_ctrl__rom
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rom_ctrl__rom
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rstmgr_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rstmgr_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rstmgr_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_core_ibex__cfg
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_core_ibex__cfg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_core_ibex__cfg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_core_ibex__cored
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_core_ibex__cored
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_core_ibex__cored
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_core_ibex__corei
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_core_ibex__corei
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_core_ibex__corei
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_dm__mem
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_dm__mem
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_dm__mem
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_dm__regs
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_dm__regs
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_dm__regs
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_dm__sba
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_dm__sba
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_dm__sba
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_plic
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_plic
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_plic
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : rv_timer
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance rv_timer
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance rv_timer
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : sensor_ctrl_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance sensor_ctrl_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sensor_ctrl_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : spi_device
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance spi_device
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance spi_device
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : spi_host0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance spi_host0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance spi_host0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : spi_host1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance spi_host1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance spi_host1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : sram_ctrl_main__ram
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance sram_ctrl_main__ram
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sram_ctrl_main__ram
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : sram_ctrl_main__regs
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance sram_ctrl_main__regs
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sram_ctrl_main__regs
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance sram_ctrl_ret_aon__ram
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sram_ctrl_ret_aon__ram
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance sram_ctrl_ret_aon__regs
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sram_ctrl_ret_aon__regs
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : sysrst_ctrl_aon
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance sysrst_ctrl_aon
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance sysrst_ctrl_aon
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : uart0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance uart0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance uart0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : uart1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance uart1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance uart1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : uart2
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance uart2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance uart2
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : uart3
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance uart3
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance uart3
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : usbdev
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance usbdev
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance usbdev
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
cp_rsp_dly |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |