Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : gpio
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_gpio 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_gpio

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : gpio
TotalCoveredPercent
Totals 33 33 100.00
Total Bits 540 540 100.00
Total Bits 0->1 270 270 100.00
Total Bits 1->0 270 270 100.00

Ports 33 33 100.00
Port Bits 540 540 100.00
Port Bits 0->1 270 270 100.00
Port Bits 1->0 270 270 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T6,T15 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_i.a_address[5:0] Yes Yes *T77,*T78,*T79 Yes T77,T78,T79 INPUT
tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T15 Yes T4,T5,T15 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T15 Yes T4,T5,T15 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T18,*T69,*T80 Yes T18,T69,T80 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T79 Yes T77,T78,T79 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T18,T2,T81 Yes T18,T2,T81 INPUT
tl_i.a_valid Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_o.a_ready Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_o.d_error Yes Yes T77,T78,T123 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T251,T252,T35 Yes T251,T252,T35 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T251,T252,T35 Yes T57,T251,T252 OUTPUT
tl_o.d_data[31:0] Yes Yes T251,T252,T35 Yes T57,T251,T252 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
tl_o.d_source[5:0] Yes Yes *T205,*T77,*T78 Yes T205,T77,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T15,*T16 Yes T4,T5,T15 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
intr_gpio_o[31:0] Yes Yes T251,T252,T35 Yes T251,T252,T35 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T57,T84,T58 Yes T57,T84,T58 INPUT
alert_rx_i[0].ping_n Yes Yes T84,T159,T86 Yes T159,T86,T156 INPUT
alert_rx_i[0].ping_p Yes Yes T159,T86,T156 Yes T84,T159,T86 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T57,T84,T58 Yes T57,T84,T58 OUTPUT
cio_gpio_i[31:0] Yes Yes T35,T36,T87 Yes T35,T36,T87 INPUT
cio_gpio_o[31:0] Yes Yes T35,T36,T87 Yes T35,T36,T3 OUTPUT
cio_gpio_en_o[31:0] Yes Yes T35,T36,T37 Yes T35,T36,T3 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%