Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513250553	59238955	0	0
DepthKnown_A	513250553	513144545	0	0
RvalidKnown_A	513250553	513144545	0	0
WreadyKnown_A	513250553	513144545	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	59238955	0	0
T4	175673	18792	0	0
T5	279890	36838	0	0
T6	50772	0	0	0
T15	376922	54785	0	0
T16	223326	29548	0	0
T52	0	143491	0	0
T61	139714	18776	0	0
T88	121265	13054	0	0
T89	120915	17876	0	0
T90	547808	67944	0	0
T91	68312	7047	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513250553	45418305	0	0
DepthKnown_A	513250553	513144545	0	0
RvalidKnown_A	513250553	513144545	0	0
WreadyKnown_A	513250553	513144545	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	45418305	0	0
T4	175673	14947	0	0
T5	279890	27267	0	0
T6	50772	0	0	0
T15	376922	45995	0	0
T16	223326	19867	0	0
T52	0	124106	0	0
T61	139714	13700	0	0
T88	121265	11004	0	0
T89	120915	13563	0	0
T90	547808	62840	0	0
T91	68312	5105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513250553	41270222	0	0
DepthKnown_A	513250553	513144545	0	0
RvalidKnown_A	513250553	513144545	0	0
WreadyKnown_A	513250553	513144545	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	41270222	0	0
T4	175673	7408	0	0
T5	279890	19427	0	0
T6	50772	0	0	0
T15	376922	38498	0	0
T16	223326	14041	0	0
T52	0	197529	0	0
T61	139714	7862	0	0
T88	121265	7492	0	0
T89	120915	11485	0	0
T90	547808	58362	0	0
T91	68312	3813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513250553	34716408	0	0
DepthKnown_A	513250553	513144545	0	0
RvalidKnown_A	513250553	513144545	0	0
WreadyKnown_A	513250553	513144545	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	34716408	0	0
T4	175673	7164	0	0
T5	279890	19044	0	0
T6	50772	0	0	0
T15	376922	38082	0	0
T16	223326	13652	0	0
T52	0	116155	0	0
T61	139714	7594	0	0
T88	121265	7276	0	0
T89	120915	11270	0	0
T90	547808	56752	0	0
T91	68312	3692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513250553	513144545	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	92281	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	92281	0	0
T4	175673	31	0	0
T5	279890	151	0	0
T6	50772	0	0	0
T15	376922	48	0	0
T16	223326	151	0	0
T52	0	34	0	0
T61	139714	26	0	0
T88	121265	106	0	0
T89	120915	15	0	0
T90	547808	1974	0	0
T91	68312	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	95427	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	95427	0	0
T4	175673	31	0	0
T5	279890	151	0	0
T6	50772	0	0	0
T15	376922	48	0	0
T16	223326	151	0	0
T52	0	34	0	0
T61	139714	26	0	0
T88	121265	106	0	0
T89	120915	15	0	0
T90	547808	1974	0	0
T91	68312	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	52891	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	52891	0	0
T4	175673	28	0	0
T5	279890	95	0	0
T6	50772	0	0	0
T15	376922	41	0	0
T16	223326	95	0	0
T52	0	5	0	0
T61	139714	23	0	0
T88	121265	105	0	0
T89	120915	14	0	0
T90	547808	1335	0	0
T91	68312	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	52891	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	52891	0	0
T4	175673	28	0	0
T5	279890	95	0	0
T6	50772	0	0	0
T15	376922	41	0	0
T16	223326	95	0	0
T52	0	5	0	0
T61	139714	23	0	0
T88	121265	105	0	0
T89	120915	14	0	0
T90	547808	1335	0	0
T91	68312	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	39390	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	39390	0	0
T4	175673	3	0	0
T5	279890	56	0	0
T6	50772	0	0	0
T15	376922	7	0	0
T16	223326	56	0	0
T52	0	29	0	0
T61	139714	3	0	0
T88	121265	1	0	0
T89	120915	1	0	0
T90	547808	639	0	0
T91	68312	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584147079	42536	0	0
DepthKnown_A	584147079	584029670	0	0
RvalidKnown_A	584147079	584029670	0	0
WreadyKnown_A	584147079	584029670	0	0
gen_passthru_fifo.paramCheckPass	2902	2902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	42536	0	0
T4	175673	3	0	0
T5	279890	56	0	0
T6	50772	0	0	0
T15	376922	7	0	0
T16	223326	56	0	0
T52	0	29	0	0
T61	139714	3	0	0
T88	121265	1	0	0
T89	120915	1	0	0
T90	547808	639	0	0
T91	68312	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584147079	584029670	0	0
T4	175673	175615	0	0
T5	279890	279773	0	0
T6	50772	50659	0	0
T15	376922	376805	0	0
T16	223326	223210	0	0
T61	139714	139652	0	0
T88	121265	121207	0	0
T89	120915	120860	0	0
T90	547808	547757	0	0
T91	68312	68254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2902	2902	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T61	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0