Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.98 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.98 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15601560100.00
ALWAYS6844100.00
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CONT_ASSIGN1659311100.00
CONT_ASSIGN1662711100.00
CONT_ASSIGN1664111100.00
ALWAYS16647203203100.00
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CONT_ASSIGN1940200
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16579 1 1
16593 1 1
16627 1 1
16641 1 1
16647 1 1
16648 1 1
16649 1 1
16650 1 1
16651 1 1
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19314 1 1
19315 1 1
19316 1 1
19317 1 1
19318 1 1
19319 1 1
19320 1 1
19321 1 1
19322 1 1
19323 1 1
19324 1 1
19325 1 1
19326 1 1
19327 1 1
19328 1 1
19329 1 1
19330 1 1
19331 1 1
19332 1 1
19333 1 1
19334 1 1
19335 1 1
19336 1 1
19337 1 1
19338 1 1
19339 1 1
19340 1 1
19341 1 1
19342 1 1
19343 1 1
19347 1 1
19348 1 1
19349 1 1
19350 1 1
19351 1 1
19352 1 1
19353 1 1
19354 1 1
19355 1 1
19356 1 1
19357 1 1
19358 1 1
19359 1 1
19360 1 1
19361 1 1
19362 1 1
19363 1 1
19364 1 1
19365 1 1
19366 1 1
19367 1 1
19368 1 1
19369 1 1
19370 1 1
19371 1 1
19372 1 1
19376 1 1
19380 1 1
19384 1 1
19388 1 1
19402 unreachable
19410 1 1
19411 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2023202199.90
Logical2023202199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1683399.74
16834-16856100.00
16856100.00
16856-17341100.00
17344-1800899.76

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 208 208 100.00
TERNARY 16852 2 2 100.00
IF 68 3 3 100.00
CASE 18222 203 203 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16852 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T16
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T303,T304,T305
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 18222 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T16
addr_hit[1] Covered T94,T97,T301
addr_hit[2] Covered T94,T97,T301
addr_hit[3] Covered T94,T97,T301
addr_hit[4] Covered T94,T97,T301
addr_hit[5] Covered T94,T97,T301
addr_hit[6] Covered T94,T97,T301
addr_hit[7] Covered T94,T97,T301
addr_hit[8] Covered T94,T97,T301
addr_hit[9] Covered T94,T97,T301
addr_hit[10] Covered T251,T252,T153
addr_hit[11] Covered T251,T252,T153
addr_hit[12] Covered T251,T252,T153
addr_hit[13] Covered T251,T252,T153
addr_hit[14] Covered T251,T252,T153
addr_hit[15] Covered T251,T252,T153
addr_hit[16] Covered T251,T252,T153
addr_hit[17] Covered T251,T252,T153
addr_hit[18] Covered T251,T252,T153
addr_hit[19] Covered T144,T251,T252
addr_hit[20] Covered T144,T251,T252
addr_hit[21] Covered T144,T251,T252
addr_hit[22] Covered T144,T251,T252
addr_hit[23] Covered T144,T251,T252
addr_hit[24] Covered T144,T251,T252
addr_hit[25] Covered T144,T251,T252
addr_hit[26] Covered T144,T251,T252
addr_hit[27] Covered T144,T251,T252
addr_hit[28] Covered T25,T26,T251
addr_hit[29] Covered T25,T26,T251
addr_hit[30] Covered T25,T26,T251
addr_hit[31] Covered T25,T26,T251
addr_hit[32] Covered T25,T26,T251
addr_hit[33] Covered T25,T26,T251
addr_hit[34] Covered T25,T26,T251
addr_hit[35] Covered T25,T26,T251
addr_hit[36] Covered T25,T26,T251
addr_hit[37] Covered T251,T252,T153
addr_hit[38] Covered T251,T252,T153
addr_hit[39] Covered T251,T252,T153
addr_hit[40] Covered T251,T252,T153
addr_hit[41] Covered T251,T252,T153
addr_hit[42] Covered T251,T252,T153
addr_hit[43] Covered T251,T252,T153
addr_hit[44] Covered T251,T252,T153
addr_hit[45] Covered T251,T252,T153
addr_hit[46] Covered T251,T252,T153
addr_hit[47] Covered T251,T252,T153
addr_hit[48] Covered T251,T252,T153
addr_hit[49] Covered T251,T252,T153
addr_hit[50] Covered T251,T252,T153
addr_hit[51] Covered T251,T252,T153
addr_hit[52] Covered T251,T252,T153
addr_hit[53] Covered T251,T252,T153
addr_hit[54] Covered T251,T252,T153
addr_hit[55] Covered T251,T252,T153
addr_hit[56] Covered T251,T252,T153
addr_hit[57] Covered T251,T252,T153
addr_hit[58] Covered T251,T252,T153
addr_hit[59] Covered T251,T252,T153
addr_hit[60] Covered T251,T252,T153
addr_hit[61] Covered T251,T252,T153
addr_hit[62] Covered T251,T252,T153
addr_hit[63] Covered T251,T252,T153
addr_hit[64] Covered T251,T252,T153
addr_hit[65] Covered T251,T252,T153
addr_hit[66] Covered T251,T252,T153
addr_hit[67] Covered T251,T252,T153
addr_hit[68] Covered T251,T252,T153
addr_hit[69] Covered T22,T251,T47
addr_hit[70] Covered T251,T47,T252
addr_hit[71] Covered T251,T47,T252
addr_hit[72] Covered T22,T251,T47
addr_hit[73] Covered T22,T251,T47
addr_hit[74] Covered T251,T47,T252
addr_hit[75] Covered T251,T252,T153
addr_hit[76] Covered T251,T252,T153
addr_hit[77] Covered T251,T252,T153
addr_hit[78] Covered T251,T252,T153
addr_hit[79] Covered T251,T252,T153
addr_hit[80] Covered T251,T252,T153
addr_hit[81] Covered T251,T252,T153
addr_hit[82] Covered T251,T252,T153
addr_hit[83] Covered T251,T252,T153
addr_hit[84] Covered T251,T252,T153
addr_hit[85] Covered T251,T252,T153
addr_hit[86] Covered T251,T216,T252
addr_hit[87] Covered T251,T216,T252
addr_hit[88] Covered T251,T252,T153
addr_hit[89] Covered T251,T216,T252
addr_hit[90] Covered T251,T216,T252
addr_hit[91] Covered T251,T216,T252
addr_hit[92] Covered T251,T252,T219
addr_hit[93] Covered T251,T252,T219
addr_hit[94] Covered T251,T252,T153
addr_hit[95] Covered T251,T252,T219
addr_hit[96] Covered T251,T252,T219
addr_hit[97] Covered T251,T252,T219
addr_hit[98] Covered T251,T252,T219
addr_hit[99] Covered T251,T252,T219
addr_hit[100] Covered T251,T252,T153
addr_hit[101] Covered T251,T252,T219
addr_hit[102] Covered T251,T252,T153
addr_hit[103] Covered T251,T252,T153
addr_hit[104] Covered T251,T252,T153
addr_hit[105] Covered T251,T252,T153
addr_hit[106] Covered T251,T252,T153
addr_hit[107] Covered T251,T222,T252
addr_hit[108] Covered T251,T222,T252
addr_hit[109] Covered T251,T252,T153
addr_hit[110] Covered T251,T222,T252
addr_hit[111] Covered T251,T222,T252
addr_hit[112] Covered T251,T222,T252
addr_hit[113] Covered T251,T222,T252
addr_hit[114] Covered T251,T222,T252
addr_hit[115] Covered T251,T252,T153
addr_hit[116] Covered T251,T222,T252
addr_hit[117] Covered T251,T252,T153
addr_hit[118] Covered T251,T252,T153
addr_hit[119] Covered T251,T252,T153
addr_hit[120] Covered T251,T252,T153
addr_hit[121] Covered T251,T252,T153
addr_hit[122] Covered T251,T252,T153
addr_hit[123] Covered T251,T252,T153
addr_hit[124] Covered T251,T252,T153
addr_hit[125] Covered T251,T252,T153
addr_hit[126] Covered T251,T252,T153
addr_hit[127] Covered T5,T16,T64
addr_hit[128] Covered T5,T16,T64
addr_hit[129] Covered T5,T16,T64
addr_hit[130] Covered T5,T16,T64
addr_hit[131] Covered T22,T251,T252
addr_hit[132] Covered T22,T251,T252
addr_hit[133] Covered T251,T252,T153
addr_hit[134] Covered T251,T252,T153
addr_hit[135] Covered T251,T252,T153
addr_hit[136] Covered T251,T252,T153
addr_hit[137] Covered T251,T252,T153
addr_hit[138] Covered T251,T252,T153
addr_hit[139] Covered T251,T252,T153
addr_hit[140] Covered T251,T252,T153
addr_hit[141] Covered T251,T252,T153
addr_hit[142] Covered T251,T252,T153
addr_hit[143] Covered T251,T252,T153
addr_hit[144] Covered T251,T252,T153
addr_hit[145] Covered T251,T252,T153
addr_hit[146] Covered T251,T252,T153
addr_hit[147] Covered T251,T252,T153
addr_hit[148] Covered T251,T252,T153
addr_hit[149] Covered T251,T252,T153
addr_hit[150] Covered T251,T252,T153
addr_hit[151] Covered T251,T252,T153
addr_hit[152] Covered T251,T252,T153
addr_hit[153] Covered T4,T61,T93
addr_hit[154] Covered T251,T252,T153
addr_hit[155] Covered T107,T251,T252
addr_hit[156] Covered T4,T5,T16
addr_hit[157] Covered T4,T5,T16
addr_hit[158] Covered T251,T252,T153
addr_hit[159] Covered T251,T252,T153
addr_hit[160] Covered T251,T252,T328
addr_hit[161] Covered T251,T252,T328
addr_hit[162] Covered T251,T252,T328
addr_hit[163] Covered T251,T252,T328
addr_hit[164] Covered T251,T252,T328
addr_hit[165] Covered T251,T252,T153
addr_hit[166] Covered T285,T251,T252
addr_hit[167] Covered T285,T251,T252
addr_hit[168] Covered T251,T252,T153
addr_hit[169] Covered T251,T252,T153
addr_hit[170] Covered T251,T252,T153
addr_hit[171] Covered T251,T252,T153
addr_hit[172] Covered T251,T111,T252
addr_hit[173] Covered T251,T252,T153
addr_hit[174] Covered T251,T252,T153
addr_hit[175] Covered T251,T316,T252
addr_hit[176] Covered T251,T252,T153
addr_hit[177] Covered T251,T252,T153
addr_hit[178] Covered T251,T252,T153
addr_hit[179] Covered T251,T252,T153
addr_hit[180] Covered T251,T252,T153
addr_hit[181] Covered T251,T252,T153
addr_hit[182] Covered T251,T316,T252
addr_hit[183] Covered T251,T252,T153
addr_hit[184] Covered T251,T316,T252
addr_hit[185] Covered T251,T252,T153
addr_hit[186] Covered T204,T205,T411
addr_hit[187] Covered T204,T205,T411
addr_hit[188] Covered T204,T205,T411
addr_hit[189] Covered T204,T205,T411
addr_hit[190] Covered T287,T630,T204
addr_hit[191] Covered T204,T205,T411
addr_hit[192] Covered T94,T97,T25
addr_hit[193] Covered T25,T26,T251
addr_hit[194] Covered T22,T251,T47
addr_hit[195] Covered T5,T16,T64
addr_hit[196] Covered T4,T5,T16
addr_hit[197] Covered T285,T251,T111
addr_hit[198] Covered T4,T5,T16
addr_hit[199] Covered T4,T5,T16
addr_hit[200] Covered T204,T248,T249
addr_hit[201] Covered T57,T58,T204
default Covered T78,T79,T82


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 584147079 176752 0 0
reAfterRv 584147079 176752 0 0
rePulse 584147079 115509 0 0
wePulse 584147079 61243 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 584147079 176752 0 0
T4 175673 21 0 0
T5 279890 44 0 0
T6 50772 0 0 0
T15 376922 0 0 0
T16 223326 44 0 0
T61 139714 8 0 0
T64 0 44 0 0
T88 121265 0 0 0
T89 120915 0 0 0
T90 547808 0 0 0
T91 68312 0 0 0
T93 0 6 0 0
T94 0 48 0 0
T95 0 8 0 0
T97 0 48 0 0
T174 0 44 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 584147079 176752 0 0
T4 175673 21 0 0
T5 279890 44 0 0
T6 50772 0 0 0
T15 376922 0 0 0
T16 223326 44 0 0
T61 139714 8 0 0
T64 0 44 0 0
T88 121265 0 0 0
T89 120915 0 0 0
T90 547808 0 0 0
T91 68312 0 0 0
T93 0 6 0 0
T94 0 48 0 0
T95 0 8 0 0
T97 0 48 0 0
T174 0 44 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 584147079 115509 0 0
T4 175673 8 0 0
T5 279890 14 0 0
T6 50772 0 0 0
T15 376922 0 0 0
T16 223326 14 0 0
T61 139714 3 0 0
T64 0 14 0 0
T88 121265 0 0 0
T89 120915 0 0 0
T90 547808 0 0 0
T91 68312 0 0 0
T93 0 2 0 0
T94 0 19 0 0
T95 0 3 0 0
T97 0 19 0 0
T174 0 14 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 584147079 61243 0 0
T4 175673 13 0 0
T5 279890 30 0 0
T6 50772 0 0 0
T15 376922 0 0 0
T16 223326 30 0 0
T61 139714 5 0 0
T64 0 30 0 0
T88 121265 0 0 0
T89 120915 0 0 0
T90 547808 0 0 0
T91 68312 0 0 0
T93 0 4 0 0
T94 0 29 0 0
T95 0 5 0 0
T97 0 29 0 0
T174 0 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%