Unified Coverage Report :: Module :: tlul_adapter_reg

Module : tlul_adapter_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	97.96			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if	93.91	97.37	78.26			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if	98.98	100.00	95.92			100.00	100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if	99.46	100.00	97.83			100.00	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if	99.46	100.00	97.83			100.00	100.00

Line Coverage for Module : tlul_adapter_reg

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
ALWAYS	95	6	6	100.00
ALWAYS	101	8	8	100.00
ALWAYS	141	6	6	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
ALWAYS	218	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
80	1	1
81	1	1
83	1	1
84	1	1
85	1	1
86	1	1
91	1	1
95	2	2
96	2	2
97	2	2
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
106	1	1
107	1	1
109	1	1
			MISSING_ELSE
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
			MISSING_ELSE
149	1	1
150	1	1
154	1	1
204	1	1
208	1	1
211	1	1
218	1	1
220	1	1
223	1	1

---

Cond Coverage for Module : tlul_adapter_reg

	Total	Covered	Percent
Conditions	49	48	97.96
Logical	49	48	97.96
Non-Logical	0	0
Event	0	0

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T15

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T52,T53,T54
1	1	Covered	T4,T5,T15

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T15
1	1	Covered	T4,T5,T15

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T18,T2,T81
1	0	Covered	T4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T81

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T15
1	0	Covered	T4,T5,T15
1	1	Covered	T4,T5,T15

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T15

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T15
1	0	Covered	T77,T78,T79
1	1	Covered	T4,T5,T15

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T15
1	0	Covered	T78,T83,T411
1	1	Covered	T4,T5,T15

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T4,T5,T15

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T4,T5,T15

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T15
0	0	1	Covered	T4,T5,T15
0	1	0	Covered	T411,T613,T511
1	0	0	Covered	T511,T527,T543

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T411,T613,T511
1	0	Covered	T411,T511,T515

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T142,T384,T385
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T4,T5,T15
0	0	0	0	1	Unreachable
0	0	0	1	0	Covered	T83,T523,T554
0	0	1	0	0	Covered	T4,T5,T15
0	1	0	0	0	Not Covered
1	0	0	0	0	Covered	T77,T79,T82

---

Branch Coverage for Module : tlul_adapter_reg

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
IF	95	4	4	100.00
IF	101	4	4	100.00
IF	218	2	2	100.00
IF	141	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))
-2-:	96	if (a_ack)
-3-:	97	if (d_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T15
0	0	1	Covered	T4,T5,T15
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	105	if (a_ack)
-3-:	109	(rd_req) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	1	Covered	T4,T5,T15
0	1	0	Covered	T4,T5,T15
0	0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	218	if (wr_req)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T15
0	Covered	T4,T5,T15

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	144	if (a_ack)
-3-:	145	(((error_i || err_internal) || wr_req)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	1	Covered	T4,T5,T15
0	1	0	Covered	T4,T5,T15
0	0	-	Covered	T4,T5,T6

---

Assert Coverage for Module : tlul_adapter_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllowedLatency_A	9719	9719	0	0
MatchedWidthAssert	9719	9719	0	0

AllowedLatency_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719	9719	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T61	4	4	0	0
T88	4	4	0	0
T89	4	4	0	0
T90	4	4	0	0
T91	4	4	0	0

MatchedWidthAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719	9719	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T61	4	4	0	0
T88	4	4	0	0
T89	4	4	0	0
T90	4	4	0	0
T91	4	4	0	0