Module Definition
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Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions494897.96
Logical494897.96
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T15

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT52,T53,T54
11CoveredT4,T5,T15

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T15
11CoveredT4,T5,T15

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT4,T5,T15
01CoveredT18,T2,T81
10CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT18,T2,T81

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT4,T5,T15
10CoveredT4,T5,T15
11CoveredT4,T5,T15

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T15

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T15
10CoveredT77,T78,T79
11CoveredT4,T5,T15

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T15
10CoveredT78,T83,T411
11CoveredT4,T5,T15

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T15

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T15

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT4,T5,T15
001CoveredT4,T5,T15
010CoveredT411,T613,T511
100CoveredT511,T527,T543

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT4,T5,T15
01CoveredT411,T613,T511
10CoveredT411,T511,T515

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10CoveredT4,T5,T15

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01CoveredT142,T384,T385
10CoveredT4,T5,T15
11CoveredT1,T2,T3

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT4,T5,T15
00001Unreachable
00010CoveredT83,T523,T554
00100CoveredT4,T5,T15
01000Not Covered
10000CoveredT77,T79,T82

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T15
0 0 1 Covered T4,T5,T15
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T15
0 1 0 Covered T4,T5,T15
0 0 - Covered T4,T5,T6


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T4,T5,T15
0 Covered T4,T5,T15


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T15
0 1 0 Covered T4,T5,T15
0 0 - Covered T4,T5,T6


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 9719 9719 0 0
MatchedWidthAssert 9719 9719 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9719 9719 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T15 4 4 0 0
T16 4 4 0 0
T61 4 4 0 0
T88 4 4 0 0
T89 4 4 0 0
T90 4 4 0 0
T91 4 4 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 9719 9719 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T15 4 4 0 0
T16 4 4 0 0
T61 4 4 0 0
T88 4 4 0 0
T89 4 4 0 0
T90 4 4 0 0
T91 4 4 0 0

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