Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_i.a_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_o.a_ready	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_error	Yes	Yes	T148,T78,T79	Yes	T78,T79,T123	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T123	Yes	T148,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T640,*T254,*T643	Yes	T640,T254,T643	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T52,*T94,*T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T84,T644	Yes	T57,T84,T644	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T159	Yes	T84,T85,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T159	Yes	T84,T85,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T84,T644	Yes	T57,T84,T644	OUTPUT
cio_rx_i	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
cio_tx_o	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T94,T97,T144	Yes	T94,T97,T144	OUTPUT
intr_tx_empty_o	Yes	Yes	T94,T97,T144	Yes	T94,T97,T144	OUTPUT
intr_rx_watermark_o	Yes	Yes	T94,T97,T144	Yes	T94,T97,T144	OUTPUT
intr_tx_done_o	Yes	Yes	T94,T97,T144	Yes	T94,T97,T144	OUTPUT
intr_rx_overflow_o	Yes	Yes	T94,T97,T144	Yes	T94,T97,T144	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_i.a_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_o.a_ready	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T640,*T254,*T643	Yes	T640,T254,T643	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T52,*T94,*T53	Yes	T52,T94,T53	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T84,T644	Yes	T57,T84,T644	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T86,T156	Yes	T84,T86,T156	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T86,T156	Yes	T84,T86,T156	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T84,T644	Yes	T57,T84,T644	OUTPUT
cio_rx_i	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
cio_tx_o	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T94,T97,T301	Yes	T94,T97,T301	OUTPUT
intr_tx_empty_o	Yes	Yes	T94,T97,T301	Yes	T94,T97,T301	OUTPUT
intr_rx_watermark_o	Yes	Yes	T94,T97,T301	Yes	T94,T97,T301	OUTPUT
intr_tx_done_o	Yes	Yes	T94,T97,T301	Yes	T94,T97,T301	OUTPUT
intr_rx_overflow_o	Yes	Yes	T94,T97,T301	Yes	T94,T97,T301	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_i.a_valid	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	INPUT
tl_o.a_ready	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T57,T58,T217	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T217,T218,T309	Yes	T57,T58,T217	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T217,*T218,*T309	Yes	T217,T218,T309	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	OUTPUT
cio_rx_i	Yes	Yes	T217,T218,T41	Yes	T19,T217,T218	INPUT
cio_tx_o	Yes	Yes	T217,T218,T320	Yes	T217,T218,T320	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
intr_tx_done_o	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
intr_rx_overflow_o	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_i.a_valid	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	INPUT
tl_o.a_ready	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	OUTPUT
tl_o.d_error	Yes	Yes	T148,T78,T79	Yes	T78,T79,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T57,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T144,T309,T319	Yes	T144,T57,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T82,T83	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T148,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T144,*T309,*T319	Yes	T144,T309,T319	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T86,T156	Yes	T84,T86,T156	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T86,T156	Yes	T84,T86,T156	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	OUTPUT
cio_rx_i	Yes	Yes	T144,T319,T321	Yes	T144,T319,T321	INPUT
cio_tx_o	Yes	Yes	T144,T319,T321	Yes	T144,T319,T321	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
intr_tx_empty_o	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
intr_rx_watermark_o	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
intr_tx_done_o	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
intr_rx_overflow_o	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_i.a_valid	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	INPUT
tl_o.a_ready	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	OUTPUT
tl_o.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T79,T123	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T57,T26	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T57,T26	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T123,T82	Yes	T78,T82,T83	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T79,T123	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T82,T83	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T25,*T26,*T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T159	Yes	T84,T85,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T159	Yes	T84,T85,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T84,T58	Yes	T57,T84,T58	OUTPUT
cio_rx_i	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
cio_tx_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_tx_empty_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_watermark_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_tx_done_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_overflow_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT

*Tests covering at least one bit in the range