Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15024 |
14553 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T18 |
2 |
1 |
0 |
0 |
T22 |
88 |
87 |
0 |
0 |
T38 |
12 |
10 |
0 |
0 |
T39 |
21 |
19 |
0 |
0 |
T40 |
13 |
11 |
0 |
0 |
T55 |
2 |
1 |
0 |
0 |
T56 |
1 |
0 |
0 |
0 |
T62 |
3 |
2 |
0 |
0 |
T63 |
3 |
2 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T73 |
28 |
27 |
0 |
0 |
T74 |
0 |
82 |
0 |
0 |
T116 |
1 |
0 |
0 |
0 |
T168 |
0 |
3 |
0 |
0 |
T175 |
0 |
3 |
0 |
0 |
T193 |
0 |
2 |
0 |
0 |
T194 |
25 |
23 |
0 |
0 |
T195 |
3 |
2 |
0 |
0 |
T196 |
11 |
10 |
0 |
0 |
T197 |
5 |
4 |
0 |
0 |
T198 |
3 |
2 |
0 |
0 |
T199 |
5 |
4 |
0 |
0 |
T200 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114883 |
113534 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T15 |
2 |
1 |
0 |
0 |
T16 |
2 |
1 |
0 |
0 |
T38 |
13 |
11 |
0 |
0 |
T39 |
22 |
20 |
0 |
0 |
T40 |
24 |
22 |
0 |
0 |
T41 |
545 |
544 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T88 |
1 |
0 |
0 |
0 |
T89 |
1 |
0 |
0 |
0 |
T90 |
1 |
0 |
0 |
0 |
T91 |
1 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T96 |
0 |
2 |
0 |
0 |
T119 |
0 |
11 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T194 |
54 |
52 |
0 |
0 |
T195 |
9 |
16 |
0 |
0 |
T196 |
7 |
18 |
0 |
0 |
T197 |
17 |
32 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
13 |
12 |
0 |
0 |
T200 |
6 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T55,T73 |
0 | 1 | Covered | T6,T55,T73 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T55,T73 |
1 | 1 | Covered | T6,T55,T73 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1028 |
895 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T18 |
2 |
1 |
0 |
0 |
T55 |
2 |
1 |
0 |
0 |
T56 |
1 |
0 |
0 |
0 |
T62 |
3 |
2 |
0 |
0 |
T63 |
3 |
2 |
0 |
0 |
T68 |
1 |
0 |
0 |
0 |
T69 |
1 |
0 |
0 |
0 |
T73 |
28 |
27 |
0 |
0 |
T74 |
0 |
82 |
0 |
0 |
T116 |
1 |
0 |
0 |
0 |
T168 |
0 |
3 |
0 |
0 |
T175 |
0 |
3 |
0 |
0 |
T193 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1747 |
744 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T15 |
2 |
1 |
0 |
0 |
T16 |
2 |
1 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T88 |
1 |
0 |
0 |
0 |
T89 |
1 |
0 |
0 |
0 |
T90 |
1 |
0 |
0 |
0 |
T91 |
1 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T96 |
0 |
2 |
0 |
0 |
T119 |
0 |
11 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T201 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T20 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T201 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1846 |
1830 |
0 |
0 |
T22 |
88 |
87 |
0 |
0 |
T23 |
123 |
122 |
0 |
0 |
T24 |
19 |
18 |
0 |
0 |
T38 |
7 |
6 |
0 |
0 |
T39 |
12 |
11 |
0 |
0 |
T40 |
9 |
8 |
0 |
0 |
T194 |
18 |
17 |
0 |
0 |
T201 |
268 |
267 |
0 |
0 |
T202 |
1193 |
1192 |
0 |
0 |
T203 |
19 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1768 |
1748 |
0 |
0 |
T38 |
9 |
8 |
0 |
0 |
T39 |
12 |
11 |
0 |
0 |
T40 |
9 |
8 |
0 |
0 |
T41 |
545 |
544 |
0 |
0 |
T42 |
545 |
544 |
0 |
0 |
T43 |
545 |
544 |
0 |
0 |
T194 |
28 |
27 |
0 |
0 |
T195 |
0 |
8 |
0 |
0 |
T196 |
0 |
12 |
0 |
0 |
T197 |
0 |
16 |
0 |
0 |
T201 |
1 |
0 |
0 |
0 |
T202 |
1 |
0 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T21,T38,T39 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T21,T38,T39 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
59 |
48 |
0 |
0 |
T38 |
5 |
4 |
0 |
0 |
T39 |
9 |
8 |
0 |
0 |
T40 |
4 |
3 |
0 |
0 |
T194 |
7 |
6 |
0 |
0 |
T195 |
3 |
2 |
0 |
0 |
T196 |
11 |
10 |
0 |
0 |
T197 |
5 |
4 |
0 |
0 |
T198 |
3 |
2 |
0 |
0 |
T199 |
5 |
4 |
0 |
0 |
T200 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117 |
102 |
0 |
0 |
T38 |
4 |
3 |
0 |
0 |
T39 |
10 |
9 |
0 |
0 |
T40 |
15 |
14 |
0 |
0 |
T194 |
26 |
25 |
0 |
0 |
T195 |
9 |
8 |
0 |
0 |
T196 |
7 |
6 |
0 |
0 |
T197 |
17 |
16 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
13 |
12 |
0 |
0 |
T200 |
6 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1780 |
1763 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
85 |
84 |
0 |
0 |
T23 |
117 |
116 |
0 |
0 |
T24 |
19 |
18 |
0 |
0 |
T38 |
11 |
10 |
0 |
0 |
T39 |
12 |
11 |
0 |
0 |
T40 |
10 |
9 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T201 |
255 |
254 |
0 |
0 |
T202 |
1150 |
1149 |
0 |
0 |
T203 |
19 |
18 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
136 |
122 |
0 |
0 |
T38 |
13 |
12 |
0 |
0 |
T39 |
18 |
17 |
0 |
0 |
T40 |
15 |
14 |
0 |
0 |
T41 |
2 |
1 |
0 |
0 |
T42 |
2 |
1 |
0 |
0 |
T43 |
2 |
1 |
0 |
0 |
T194 |
15 |
14 |
0 |
0 |
T195 |
11 |
10 |
0 |
0 |
T196 |
11 |
10 |
0 |
0 |
T197 |
15 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T19,T20,T21 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
66 |
53 |
0 |
0 |
T38 |
4 |
3 |
0 |
0 |
T39 |
9 |
8 |
0 |
0 |
T40 |
2 |
1 |
0 |
0 |
T194 |
5 |
4 |
0 |
0 |
T195 |
6 |
5 |
0 |
0 |
T196 |
8 |
7 |
0 |
0 |
T197 |
13 |
12 |
0 |
0 |
T198 |
3 |
2 |
0 |
0 |
T199 |
9 |
8 |
0 |
0 |
T200 |
4 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116 |
101 |
0 |
0 |
T38 |
9 |
8 |
0 |
0 |
T39 |
13 |
12 |
0 |
0 |
T40 |
12 |
11 |
0 |
0 |
T194 |
15 |
14 |
0 |
0 |
T195 |
11 |
10 |
0 |
0 |
T196 |
10 |
9 |
0 |
0 |
T197 |
14 |
13 |
0 |
0 |
T198 |
6 |
5 |
0 |
0 |
T199 |
15 |
14 |
0 |
0 |
T200 |
6 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T38,T39 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T24 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2172 |
2156 |
0 |
0 |
T22 |
234 |
233 |
0 |
0 |
T23 |
246 |
245 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
8 |
7 |
0 |
0 |
T39 |
11 |
10 |
0 |
0 |
T40 |
10 |
9 |
0 |
0 |
T194 |
18 |
17 |
0 |
0 |
T195 |
0 |
12 |
0 |
0 |
T196 |
0 |
15 |
0 |
0 |
T201 |
382 |
381 |
0 |
0 |
T202 |
1177 |
1176 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
125 |
114 |
0 |
0 |
T38 |
23 |
22 |
0 |
0 |
T39 |
11 |
10 |
0 |
0 |
T40 |
8 |
7 |
0 |
0 |
T194 |
18 |
17 |
0 |
0 |
T195 |
7 |
6 |
0 |
0 |
T196 |
14 |
13 |
0 |
0 |
T197 |
13 |
12 |
0 |
0 |
T198 |
4 |
3 |
0 |
0 |
T199 |
16 |
15 |
0 |
0 |
T200 |
10 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T21,T38 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
76 |
61 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
3 |
2 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T38 |
2 |
1 |
0 |
0 |
T39 |
6 |
5 |
0 |
0 |
T194 |
8 |
7 |
0 |
0 |
T195 |
4 |
3 |
0 |
0 |
T196 |
14 |
13 |
0 |
0 |
T197 |
0 |
11 |
0 |
0 |
T201 |
3 |
2 |
0 |
0 |
T202 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109 |
97 |
0 |
0 |
T38 |
21 |
20 |
0 |
0 |
T39 |
7 |
6 |
0 |
0 |
T40 |
8 |
7 |
0 |
0 |
T194 |
16 |
15 |
0 |
0 |
T195 |
8 |
7 |
0 |
0 |
T196 |
12 |
11 |
0 |
0 |
T197 |
14 |
13 |
0 |
0 |
T198 |
5 |
4 |
0 |
0 |
T199 |
13 |
12 |
0 |
0 |
T200 |
3 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2122 |
2104 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
232 |
231 |
0 |
0 |
T23 |
240 |
239 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
10 |
9 |
0 |
0 |
T39 |
14 |
13 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T194 |
0 |
15 |
0 |
0 |
T195 |
0 |
13 |
0 |
0 |
T196 |
0 |
15 |
0 |
0 |
T201 |
370 |
369 |
0 |
0 |
T202 |
1134 |
1133 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
522 |
508 |
0 |
0 |
T38 |
10 |
9 |
0 |
0 |
T39 |
3 |
2 |
0 |
0 |
T40 |
18 |
17 |
0 |
0 |
T41 |
136 |
135 |
0 |
0 |
T42 |
164 |
163 |
0 |
0 |
T43 |
117 |
116 |
0 |
0 |
T194 |
16 |
15 |
0 |
0 |
T195 |
5 |
4 |
0 |
0 |
T196 |
14 |
13 |
0 |
0 |
T197 |
11 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T41,T42 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
79 |
63 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
3 |
2 |
0 |
0 |
T23 |
3 |
2 |
0 |
0 |
T38 |
4 |
3 |
0 |
0 |
T39 |
8 |
7 |
0 |
0 |
T40 |
8 |
7 |
0 |
0 |
T194 |
8 |
7 |
0 |
0 |
T195 |
0 |
6 |
0 |
0 |
T196 |
0 |
7 |
0 |
0 |
T201 |
3 |
2 |
0 |
0 |
T202 |
3 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105 |
90 |
0 |
0 |
T38 |
13 |
12 |
0 |
0 |
T39 |
3 |
2 |
0 |
0 |
T40 |
16 |
15 |
0 |
0 |
T194 |
13 |
12 |
0 |
0 |
T195 |
7 |
6 |
0 |
0 |
T196 |
8 |
7 |
0 |
0 |
T197 |
15 |
14 |
0 |
0 |
T198 |
7 |
6 |
0 |
0 |
T199 |
15 |
14 |
0 |
0 |
T200 |
3 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T19,T2 |
0 | 1 | Covered | T19,T20,T41 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T19,T2 |
1 | 1 | Covered | T19,T20,T41 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1833 |
1812 |
0 |
0 |
T38 |
23 |
22 |
0 |
0 |
T39 |
14 |
13 |
0 |
0 |
T40 |
5 |
4 |
0 |
0 |
T41 |
546 |
545 |
0 |
0 |
T42 |
546 |
545 |
0 |
0 |
T43 |
546 |
545 |
0 |
0 |
T194 |
27 |
26 |
0 |
0 |
T195 |
0 |
28 |
0 |
0 |
T196 |
0 |
19 |
0 |
0 |
T197 |
0 |
11 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1676 |
1649 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
1 |
0 |
0 |
0 |
T22 |
52 |
51 |
0 |
0 |
T23 |
88 |
87 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
0 |
8 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T194 |
0 |
12 |
0 |
0 |
T195 |
0 |
8 |
0 |
0 |
T196 |
0 |
16 |
0 |
0 |
T201 |
229 |
228 |
0 |
0 |
T202 |
0 |
1176 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T19,T2 |
0 | 1 | Covered | T19,T20,T41 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T19,T2 |
1 | 1 | Covered | T19,T20,T41 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1832 |
1811 |
0 |
0 |
T38 |
24 |
23 |
0 |
0 |
T39 |
12 |
11 |
0 |
0 |
T40 |
5 |
4 |
0 |
0 |
T41 |
546 |
545 |
0 |
0 |
T42 |
546 |
545 |
0 |
0 |
T43 |
546 |
545 |
0 |
0 |
T194 |
28 |
27 |
0 |
0 |
T195 |
0 |
29 |
0 |
0 |
T196 |
0 |
16 |
0 |
0 |
T197 |
0 |
12 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1668 |
1641 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
1 |
0 |
0 |
0 |
T22 |
52 |
51 |
0 |
0 |
T23 |
88 |
87 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T39 |
0 |
11 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T194 |
0 |
11 |
0 |
0 |
T195 |
0 |
9 |
0 |
0 |
T196 |
0 |
14 |
0 |
0 |
T201 |
229 |
228 |
0 |
0 |
T202 |
0 |
1176 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T2,T20 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T2,T20 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165 |
138 |
0 |
0 |
T38 |
11 |
10 |
0 |
0 |
T39 |
0 |
19 |
0 |
0 |
T40 |
0 |
17 |
0 |
0 |
T41 |
2 |
1 |
0 |
0 |
T42 |
2 |
1 |
0 |
0 |
T43 |
2 |
1 |
0 |
0 |
T194 |
0 |
15 |
0 |
0 |
T195 |
0 |
12 |
0 |
0 |
T196 |
0 |
12 |
0 |
0 |
T197 |
0 |
7 |
0 |
0 |
T201 |
1 |
0 |
0 |
0 |
T202 |
1 |
0 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1607 |
1581 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
50 |
49 |
0 |
0 |
T23 |
82 |
81 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
T39 |
0 |
12 |
0 |
0 |
T40 |
0 |
11 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T194 |
0 |
12 |
0 |
0 |
T195 |
0 |
11 |
0 |
0 |
T196 |
0 |
9 |
0 |
0 |
T201 |
217 |
216 |
0 |
0 |
T202 |
0 |
1133 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T2,T20 |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T2,T20 |
1 | 1 | Covered | T22,T23,T19 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166 |
139 |
0 |
0 |
T38 |
12 |
11 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
T40 |
0 |
17 |
0 |
0 |
T41 |
2 |
1 |
0 |
0 |
T42 |
2 |
1 |
0 |
0 |
T43 |
2 |
1 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T195 |
0 |
12 |
0 |
0 |
T196 |
0 |
12 |
0 |
0 |
T197 |
0 |
7 |
0 |
0 |
T201 |
1 |
0 |
0 |
0 |
T202 |
1 |
0 |
0 |
0 |
T203 |
1 |
0 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
T205 |
1 |
0 |
0 |
0 |
T206 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1608 |
1582 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
50 |
49 |
0 |
0 |
T23 |
82 |
81 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
T39 |
0 |
9 |
0 |
0 |
T40 |
0 |
11 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T194 |
0 |
14 |
0 |
0 |
T195 |
0 |
12 |
0 |
0 |
T196 |
0 |
9 |
0 |
0 |
T201 |
217 |
216 |
0 |
0 |
T202 |
0 |
1133 |
0 |
0 |
T204 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T2,T20 |
0 | 1 | Covered | T19,T20,T38 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T20 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T2,T20 |
1 | 1 | Covered | T19,T20,T38 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196 |
178 |
0 |
0 |
T38 |
37 |
36 |
0 |
0 |
T39 |
10 |
9 |
0 |
0 |
T40 |
22 |
21 |
0 |
0 |
T194 |
22 |
21 |
0 |
0 |
T195 |
17 |
16 |
0 |
0 |
T196 |
13 |
12 |
0 |
0 |
T197 |
11 |
10 |
0 |
0 |
T198 |
9 |
8 |
0 |
0 |
T199 |
26 |
25 |
0 |
0 |
T200 |
21 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25928 |
25898 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T22 |
267 |
266 |
0 |
0 |
T23 |
280 |
279 |
0 |
0 |
T24 |
18 |
17 |
0 |
0 |
T26 |
4014 |
4013 |
0 |
0 |
T47 |
20 |
19 |
0 |
0 |
T201 |
417 |
416 |
0 |
0 |
T202 |
1192 |
1191 |
0 |
0 |
T207 |
4019 |
4018 |
0 |
0 |
T208 |
2354 |
2353 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T2,T20 |
0 | 1 | Covered | T19,T20,T38 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T20 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T18,T2,T20 |
1 | 1 | Covered | T19,T20,T38 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
195 |
177 |
0 |
0 |
T38 |
33 |
32 |
0 |
0 |
T39 |
10 |
9 |
0 |
0 |
T40 |
20 |
19 |
0 |
0 |
T194 |
25 |
24 |
0 |
0 |
T195 |
18 |
17 |
0 |
0 |
T196 |
13 |
12 |
0 |
0 |
T197 |
12 |
11 |
0 |
0 |
T198 |
9 |
8 |
0 |
0 |
T199 |
27 |
26 |
0 |
0 |
T200 |
20 |
19 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25924 |
25894 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T22 |
267 |
266 |
0 |
0 |
T23 |
280 |
279 |
0 |
0 |
T24 |
18 |
17 |
0 |
0 |
T26 |
4014 |
4013 |
0 |
0 |
T47 |
20 |
19 |
0 |
0 |
T201 |
417 |
416 |
0 |
0 |
T202 |
1192 |
1191 |
0 |
0 |
T207 |
4019 |
4018 |
0 |
0 |
T208 |
2354 |
2353 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T88,T18,T19 |
0 | 1 | Covered | T88,T22,T23 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T88,T18,T19 |
1 | 1 | Covered | T88,T22,T23 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
710 |
668 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T41 |
0 |
131 |
0 |
0 |
T42 |
0 |
156 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T88 |
2 |
1 |
0 |
0 |
T209 |
2 |
1 |
0 |
0 |
T210 |
0 |
7 |
0 |
0 |
T211 |
0 |
7 |
0 |
0 |
T212 |
0 |
1 |
0 |
0 |
T213 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25862 |
25830 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T22 |
264 |
263 |
0 |
0 |
T23 |
274 |
273 |
0 |
0 |
T24 |
18 |
17 |
0 |
0 |
T26 |
4014 |
4013 |
0 |
0 |
T47 |
20 |
19 |
0 |
0 |
T201 |
404 |
403 |
0 |
0 |
T202 |
0 |
1148 |
0 |
0 |
T207 |
4019 |
4018 |
0 |
0 |
T208 |
0 |
2353 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T88,T18,T19 |
0 | 1 | Covered | T88,T22,T23 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T19 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T88,T18,T19 |
1 | 1 | Covered | T88,T22,T23 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
699 |
657 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T41 |
0 |
131 |
0 |
0 |
T42 |
0 |
156 |
0 |
0 |
T81 |
1 |
0 |
0 |
0 |
T88 |
2 |
1 |
0 |
0 |
T209 |
2 |
1 |
0 |
0 |
T210 |
0 |
7 |
0 |
0 |
T211 |
0 |
7 |
0 |
0 |
T212 |
0 |
1 |
0 |
0 |
T213 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25865 |
25833 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
2 |
1 |
0 |
0 |
T22 |
264 |
263 |
0 |
0 |
T23 |
274 |
273 |
0 |
0 |
T24 |
18 |
17 |
0 |
0 |
T26 |
4014 |
4013 |
0 |
0 |
T47 |
20 |
19 |
0 |
0 |
T201 |
404 |
403 |
0 |
0 |
T202 |
0 |
1148 |
0 |
0 |
T207 |
4019 |
4018 |
0 |
0 |
T208 |
0 |
2353 |
0 |
0 |