Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T77,T148,T79	Yes	T77,T148,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T77,T78,T123	Yes	T77,T78,T123	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T64,T223,T102	Yes	T64,T223,T102	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T64,T223,T102	Yes	T64,T223,T102	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T18,T206,T77	Yes	T18,T206,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T18,T206,T77	Yes	T18,T206,T77	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T5,T16,T64	Yes	T5,T16,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T77,*T148,T78	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T148,T78	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T148,T78	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T75,T80	Yes	T18,T75,T80	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T18,*T69,*T75	Yes	T18,T69,T75	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T18,T69,T75	Yes	T18,T69,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T2,T78,T82	Yes	T2,T78,T82	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T2,T78,*T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T2,T77,T148	Yes	T2,T77,T148	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T77,T79,T82	Yes	T82,T83,T409	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T78,T82,T83	Yes	T77,T78,T82	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T77,T78	Yes	T2,T78,T82	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T2,T78,T82	Yes	T2,T77,T78	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T2,T78,T82	Yes	T2,T77,T78	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T77,T78,T82	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T2,*T77,*T78	Yes	T2,T78,T82	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T2,T78,T79	Yes	T2,T78,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T69,*T80,*T253	Yes	T69,T80,T253	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T15	Yes	T5,T15,T16	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T69,T80,T253	Yes	T69,T80,T253	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T5,T15,T16	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T69,*T80,*T253	Yes	T69,T80,T253	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T5,T15,T16	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T69,T80,T2	Yes	T69,T80,T2	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T73	Yes	T52,T53,T73	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T2	Yes	T57,T58,T2	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T57,T58,T2	Yes	T57,T58,T2	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T2,*T78,*T79	Yes	T2,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T378,T266,T379	Yes	T378,T266,T379	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T78,T79	Yes	T57,T58,T2	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T378,T266,T2	Yes	T57,T378,T58	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T2,T78,*T79	Yes	T2,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T342,*T266,*T2	Yes	T378,T342,T266	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T57,T378,T58	Yes	T57,T378,T58	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_peri_i.d_error	Yes	Yes	T16,T64,T223	Yes	T16,T64,T223	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_peri_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T18,*T69,*T2	Yes	T18,T69,T80	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T22,T23,T201	Yes	T22,T23,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T22,T23,T153	Yes	T22,T23,T153	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T23,T153	Yes	T22,T57,T58	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T22,T23,T153	Yes	T22,T23,T153	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T148,T78,T79	Yes	T78,T79,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T148,T78,T79	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T22,*T23,*T153	Yes	T22,T23,T153	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T22,T57,T58	Yes	T22,T57,T58	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T153,T154,T155	Yes	T153,T154,T155	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T153,T154,T155	Yes	T57,T58,T153	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T153,T154,T155	Yes	T153,T154,T155	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T153,*T154,*T155	Yes	T153,T154,T155	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T77,T78,T123	Yes	T77,T78,T123	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	INPUT
tl_usbdev_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T76,T370,T60	Yes	T76,T370,T60	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T370,T60	Yes	T76,T370,T60	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T57,T1,T58	Yes	T1,T28,T76	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T57,*T1,*T58	Yes	T1,T28,T76	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T57,T1,T58	Yes	T57,T1,T58	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T15	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T5,T15,T89	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T82,T83	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T205,T77,T148	Yes	T205,T77,T148	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T205,T78,*T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T15	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T285,T286,T358	Yes	T285,T286,T358	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	INPUT
tl_hmac_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T52,*T53,*T285	Yes	T52,T53,T285	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T52,T53,T285	Yes	T52,T53,T285	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T152,T57,T403	Yes	T152,T57,T403	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T152,T57,T403	Yes	T152,T57,T403	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T205,*T77,*T78	Yes	T205,T77,T78	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T403,T224,T404	Yes	T403,T224,T404	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	INPUT
tl_kmac_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T15,T96,T152	Yes	T96,T403,T224	INPUT
tl_kmac_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T205,*T77,*T78	Yes	T205,T77,T78	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T15,*T96,*T152	Yes	T96,T403,T224	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T15,T90,T57	Yes	T15,T90,T57	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T90,T57	Yes	T15,T90,T57	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T15,T90,T57	Yes	T15,T90,T57	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T82	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	INPUT
tl_aes_i.d_error	Yes	Yes	T148,T78,T79	Yes	T148,T78,T79	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T90,T635	Yes	T15,T90,T57	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T90,T223,T635	Yes	T15,T90,T223	INPUT
tl_aes_i.d_sink	Yes	Yes	T148,T78,T79	Yes	T148,T78,T79	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T148,*T78,*T79	Yes	T148,T78,T79	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T223	Yes	T15,T90,T223	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T15,T90,T223	Yes	T15,T90,T223	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T77,T79,T82	Yes	T148,T79,T82	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T91	Yes	T15,T90,T91	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T90	Yes	T4,T5,T15	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T148,T78,T82	Yes	T77,T78,T79	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T205,*T148,*T78	Yes	T205,T77,T78	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T78,T123,T82	Yes	T148,T78,T79	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T91	Yes	T15,T90,T91	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T90	Yes	T4,T5,T15	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T152	Yes	T15,T90,T152	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_edn0_i.d_error	Yes	Yes	T77,T78,T82	Yes	T78,T123,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T90	Yes	T4,T5,T15	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T15,T90	Yes	T4,T5,T15	INPUT
tl_edn0_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T78,T79,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T205,*T77,*T78	Yes	T205,T78,T79	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T77,T78,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T152	Yes	T15,T90,T152	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_edn1_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T152	Yes	T15,T90,T152	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T15,T90,T152	Yes	T15,T90,T152	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T78,T79,T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T77,T78,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T77	Yes	T204,T205,T78	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T16	Yes	T4,T5,T16	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T18,*T81,*T206	Yes	T18,T81,T206	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	INPUT
tl_otbn_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	INPUT
tl_otbn_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T18,*T81,*T206	Yes	T18,T81,T206	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T15,*T90,*T52	Yes	T15,T90,T52	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T15,T90,T52	Yes	T15,T90,T52	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T15,T96,T152	Yes	T15,T96,T152	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	INPUT
tl_keymgr_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T78,T82,T83	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T15,*T52,*T96	Yes	T15,T52,T96	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T15,T52,T96	Yes	T15,T52,T96	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T2,*T254,*T77	Yes	T2,T254,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T2,T77,T78	Yes	T2,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T90	Yes	T4,T5,T90	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T2,*T77,*T78	Yes	T2,T254,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T253,*T204,*T205	Yes	T253,T204,T205	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T204,T183,T205	Yes	T204,T183,T205	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T114,T115,T17	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T114,T115,T17	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T253,T204,T205	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T114,*T115,*T282	Yes	T114,T115,T282	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T15	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range