Module Definition
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Module : prim_packer_fifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.93 100.00 90.00 85.71 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo 68.93 100.00 90.00 85.71 0.00

Line Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 unreachable
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1


Cond Coverage for Module : prim_packer_fifo
TotalCoveredPercent
Conditions403690.00
Logical403690.00
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T15

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11CoveredT4,T5,T15

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T15

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T15

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11CoveredT4,T5,T15

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T15

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T15

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT4,T5,T15
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T6

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T15

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T6

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T6

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 14 12 85.71
TERNARY 142 4 3 75.00
TERNARY 147 3 2 66.67
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T15
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T15
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 513250553 0 0 1002
ValidOPairedWithReadyI_A 513250553 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513250553 0 0 1002

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513250553 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%