Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_main_o.d_error	Yes	Yes	T16,T64,T223	Yes	T16,T64,T223	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_main_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T18,*T69,*T2	Yes	T18,T69,T80	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_uart0_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_uart0_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T640,*T254,*T643	Yes	T640,T254,T643	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T52,*T94,*T53	Yes	T52,T94,T53	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T52,T94,T53	Yes	T52,T94,T53	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	INPUT
tl_uart1_i.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T82	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T217,T218,T309	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T218,T309	Yes	T57,T58,T217	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T217,T218,T309	Yes	T57,T58,T217	INPUT
tl_uart1_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T82	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T217,*T218,*T309	Yes	T217,T218,T309	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T57,T58,T217	Yes	T57,T58,T217	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	INPUT
tl_uart2_i.d_error	Yes	Yes	T148,T78,T79	Yes	T78,T79,T82	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T309,T319	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T144,T309,T319	Yes	T144,T57,T58	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T144,T309,T319	Yes	T144,T57,T58	INPUT
tl_uart2_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T82,T83	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T148,T78,T82	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T144,*T309,*T319	Yes	T144,T309,T319	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T144,T57,T58	Yes	T144,T57,T58	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	INPUT
tl_uart3_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T79,T123	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T57,T26	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T57,T26	INPUT
tl_uart3_i.d_sink	Yes	Yes	T78,T123,T82	Yes	T78,T82,T83	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T79,T123	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T82,T83	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T25,*T26,*T27	Yes	T25,T26,T27	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T25,T57,T26	Yes	T25,T57,T26	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T251,T216,T252	Yes	T251,T216,T252	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T251,T216,T252	Yes	T251,T216,T252	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T57,T251,T216	Yes	T57,T251,T216	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T57,T251,T216	Yes	T57,T251,T216	INPUT
tl_i2c0_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T251,T216,T252	Yes	T251,T216,T252	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T251,T216,T252	Yes	T57,T251,T216	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T251,T216,T252	Yes	T57,T251,T216	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T82	Yes	T205,T78,T79	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T251,*T216,*T252	Yes	T251,T216,T252	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T57,T251,T216	Yes	T57,T251,T216	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T251,T252,T219	Yes	T251,T252,T219	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T251,T252,T219	Yes	T251,T252,T219	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T57,T251,T252	Yes	T57,T251,T252	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T57,T251,T252	Yes	T57,T251,T252	INPUT
tl_i2c1_i.d_error	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T251,T252,T219	Yes	T251,T252,T219	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T251,T252,T219	Yes	T57,T251,T252	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T251,T252,T219	Yes	T57,T251,T252	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T251,*T252,*T219	Yes	T251,T252,T219	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T57,T251,T252	Yes	T57,T251,T252	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T251,T222,T252	Yes	T251,T222,T252	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T251,T222,T252	Yes	T251,T222,T252	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T57,T251,T222	Yes	T57,T251,T222	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T57,T251,T222	Yes	T57,T251,T222	INPUT
tl_i2c2_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T82,T83	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T251,T222,T252	Yes	T251,T222,T252	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T251,T222,T252	Yes	T57,T251,T222	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T251,T222,T252	Yes	T57,T251,T222	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T205,*T77,*T78	Yes	T205,T78,T79	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T251,*T222,*T252	Yes	T251,T222,T252	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T57,T251,T222	Yes	T57,T251,T222	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T153,T154,T155	Yes	T153,T154,T155	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T153,T154,T155	Yes	T153,T154,T155	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	INPUT
tl_pattgen_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T153,T154,T155	Yes	T153,T154,T155	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T153,T154,T155	Yes	T57,T58,T153	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T153,T154,T155	Yes	T57,T58,T153	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T153,*T154,*T155	Yes	T153,T154,T155	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T57,T58,T153	Yes	T57,T58,T153	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T145,T221,T2	Yes	T145,T221,T2	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T145,T221,T2	Yes	T145,T221,T2	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T57,T58,T145	Yes	T57,T58,T145	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T57,T58,T145	Yes	T57,T58,T145	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T148,T78,T82	Yes	T148,T78,T79	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T145,T221,T2	Yes	T145,T221,T2	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T145,T221,T2	Yes	T57,T58,T145	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T145,T221,T2	Yes	T57,T58,T145	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T148,T78,T79	Yes	T148,T78,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T2,*T148,T78	Yes	T2,T148,T78	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T148,T78,T79	Yes	T148,T78,T123	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T145,*T221,*T2	Yes	T145,T221,T2	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T57,T58,T145	Yes	T57,T58,T145	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_gpio_i.d_error	Yes	Yes	T77,T78,T123	Yes	T77,T78,T82	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T251,T252,T35	Yes	T251,T252,T35	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T251,T252,T35	Yes	T57,T251,T252	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T251,T252,T35	Yes	T57,T251,T252	INPUT
tl_gpio_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T205,*T77,*T78	Yes	T205,T77,T78	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T15,*T16	Yes	T4,T5,T15	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T22,T26,T47	Yes	T22,T26,T47	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T22,T26,T47	Yes	T22,T26,T47	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T22,T57,T26	Yes	T22,T57,T26	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T22,T57,T26	Yes	T22,T57,T26	INPUT
tl_spi_device_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T22,T26,T47	Yes	T22,T26,T47	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T26,T47	Yes	T22,T26,T47	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T22,T57,T26	Yes	T22,T26,T47	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T22,*T57,*T26	Yes	T22,T26,T47	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T22,T57,T26	Yes	T22,T57,T26	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T250,T145,T153	Yes	T250,T145,T153	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T250,T145,T153	Yes	T250,T145,T153	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T57,T250,T58	Yes	T57,T250,T58	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T57,T250,T58	Yes	T57,T250,T58	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T78,T123,T82	Yes	T78,T82,T83	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T250,T153,T154	Yes	T250,T153,T154	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T250,T145,T153	Yes	T57,T250,T58	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T250,T145,T387	Yes	T57,T250,T58	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T250,*T145,*T153	Yes	T250,T145,T153	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T57,T250,T58	Yes	T57,T250,T58	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T61,T52	Yes	T4,T61,T52	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T61,T52	Yes	T4,T61,T52	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T15,T61	Yes	T4,T15,T61	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T15,T61	Yes	T4,T15,T61	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T148,T78,T82	Yes	T148,T78,T82	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T61,T52	Yes	T4,T61,T52	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T61,T52	Yes	T4,T15,T61	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T61,T52	Yes	T4,T15,T61	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T2,*T148,*T78	Yes	T2,T78,T79	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T148,T78,T79	Yes	T148,T78,T82	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T61,*T52	Yes	T4,T61,T52	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T15,T61	Yes	T4,T15,T61	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T82	Yes	T2,T78,T79	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T94,T97,T55	Yes	T94,T97,T55	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T94,T97,T55	Yes	T94,T97,T55	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T78,T79,T82	Yes	T148,T78,T79	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T94,T97,T25	Yes	T94,T97,T25	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T149,T150,T639	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T94,*T97,*T55	Yes	T94,T97,T55	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T2,*T78,*T82	Yes	T2,T78,T79	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T77,T148,T78	Yes	T148,T78,T79	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T148,T78,T79	Yes	T78,T79,T123	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T149,*T150,*T151	Yes	T149,T150,T151	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T123	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T15,*T96,*T152	Yes	T15,T96,T152	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T15	Yes	T5,T15,T16	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T5,T15,T16	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T78,T82,T83	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T82	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T5,T15,T16	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T63,T193	Yes	T57,T62,T63	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T69,*T307,*T308	Yes	T69,T307,T308	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T96,*T17,*T26	Yes	T52,T96,T53	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T52,T96,T53	Yes	T52,T96,T53	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T148,T78,T79	Yes	T78,T79,T83	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T53,T120,T54	Yes	T53,T120,T54	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T120,T54	Yes	T53,T120,T54	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T148,T78,T79	Yes	T148,T78,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T148	Yes	T204,T205,T78	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T148,T78,T79	Yes	T78,T79,T82	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T15,*T16	Yes	T4,T5,T15	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T16,T61	Yes	T5,T15,T16	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T78,*T123,*T82	Yes	T78,T79,T123	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T15,*T16	Yes	T5,T15,T16	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T114,T115,T180	Yes	T114,T115,T180	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T114,T115,T17	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T114,T115,T17	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T78,T123,T82	Yes	T78,T79,T123	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T123	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T114,*T115,*T180	Yes	T114,T115,T180	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T52,T53,T114	Yes	T52,T53,T114	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T15	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T15	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T82,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T18,*T81,*T254	Yes	T18,T81,T254	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T15	Yes	T4,T5,T15	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T78,T82,T83	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T80,T253,T640	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T78,T82,T83	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T16	Yes	T4,T5,T16	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T88,T44,T1	Yes	T88,T44,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T88,T44,T1	Yes	T88,T44,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T88,T57,T44	Yes	T88,T57,T44	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T88,T57,T44	Yes	T88,T57,T44	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T78,T79,T123	Yes	T78,T79,T82	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T88,T44,T1	Yes	T88,T44,T1	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T1,T300	Yes	T57,T44,T1	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T88,T44,T300	Yes	T88,T57,T44	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T204,*T205,*T78	Yes	T204,T205,T78	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T44,*T1,*T300	Yes	T88,T44,T1	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T88,T57,T44	Yes	T88,T57,T44	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T107,T251,T1	Yes	T107,T251,T1	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T107,T251,T1	Yes	T107,T251,T1	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T57,T107,T251	Yes	T57,T107,T251	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T57,T107,T251	Yes	T57,T107,T251	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T78,T82,T83	Yes	T78,T79,T82	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T107,T251,T1	Yes	T107,T251,T1	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T251,T1	Yes	T57,T107,T251	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T107,T1,T7	Yes	T57,T107,T251	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T79,T82	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T78,T82,T83	Yes	T78,T82,T83	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T107,*T251,*T1	Yes	T107,T251,T1	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T57,T107,T251	Yes	T57,T107,T251	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T18,*T69,*T80	Yes	T18,T69,T80	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T18,T2,T81	Yes	T18,T2,T81	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
tl_ast_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T82	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T15,T16	Yes	T4,T5,T15	INPUT
tl_ast_i.d_sink	Yes	Yes	T78,T79,T82	Yes	T78,T79,T123	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T83	Yes	T78,T79,T82	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T78,T79,T123	Yes	T78,T79,T82	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T82	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T15	Yes	T4,T5,T15	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range