Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev_aon_wake
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.98 100.00 93.18 94.74 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake 96.98 100.00 93.18 94.74 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.98 100.00 93.18 94.74 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.43 100.00 95.59 98.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 99.12 82.53 98.84 77.51 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
filter_activity 100.00 100.00 100.00 100.00
filter_bus_reset 100.00 100.00 100.00 100.00
filter_sense 100.00 100.00 100.00 100.00
u_pullup_en_cdc 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_aon_wake
Line No.TotalCoveredPercent
TOTAL3939100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12011100.00
ALWAYS12399100.00
ALWAYS13766100.00
ALWAYS16333100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
ALWAYS19255100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
80 1 1
81 1 1
106 1 1
108 1 1
110 1 1
113 1 1
114 1 1
115 1 1
118 1 1
120 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
129 1 1
130 1 1
131 1 1
132 1 1
137 1 1
139 1 1
142 1 1
143 1 1
MISSING_ELSE
151 1 1
152 1 1
MISSING_ELSE
163 1 1
164 1 1
166 1 1
170 1 1
186 1 1
188 1 1
192 1 1
193 1 1
194 1 1
196 1 1
197 1 1
201 1 1
203 1 1

Cond Coverage for Module : usbdev_aon_wake
TotalCoveredPercent
Conditions444193.18
Logical444193.18
Non-Logical00
Event00

 LINE       54
 EXPRESSION ((usb_dp_i != usb_dppullup_en_o) | (usb_dn_i != usb_dnpullup_en_o))
             ---------------1---------------   ---------------2---------------
-1--2-StatusTests
00CoveredT1,T28,T19
01CoveredT33,T38,T39
10CoveredT4,T5,T6 

 LINE       54
 SUB-EXPRESSION (usb_dp_i != usb_dppullup_en_o)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T28,T19
1CoveredT4,T5,T6 

 LINE       54
 SUB-EXPRESSION (usb_dn_i != usb_dnpullup_en_o)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT32,T33,T34 

 LINE       80
 EXPRESSION (((~usb_dp_i)) & ((~usb_dn_i)))
             ------1------   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT76,T60,T32
11CoveredT19,T76,T60 

 LINE       106
 EXPRESSION ((event_not_idle | bus_not_idle_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT28,T60,T13
10CoveredT4,T5,T6
11CoveredT1,T13,T14 

 LINE       106
 SUB-EXPRESSION (event_not_idle | bus_not_idle_q)
                 -------1------   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT13,T14,T99
10CoveredT4,T5,T6 

 LINE       108
 EXPRESSION ((event_bus_reset | bus_reset_q) & wake_detect_active_q)
             ---------------1---------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T28,T60
10CoveredT76,T60,T373
11CoveredT60 

 LINE       108
 SUB-EXPRESSION (event_bus_reset | bus_reset_q)
                 -------1-------   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT76,T60,T373 

 LINE       110
 EXPRESSION ((event_sense_lost | sense_lost_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT60
10CoveredT4,T5,T6
11CoveredT1,T28,T13 

 LINE       110
 SUB-EXPRESSION (event_sense_lost | sense_lost_q)
                 --------1-------   ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT4,T5,T6 

 LINE       118
 EXPRESSION (wake_detect_active_q & (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q))
             ----------1---------   ---------------------------------2--------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT60
11CoveredT1,T28,T60 

 LINE       118
 SUB-EXPRESSION (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q)
                 -------1------   -------2-------   --------3-------   -----4----
-1--2--3--4-StatusTests
0000CoveredT4,T5,T6
0001Not Covered
0010CoveredT4,T5,T6
0100CoveredT76,T60,T373
1000CoveredT377,T33,T34 

 LINE       186
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_aon)
             ----------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T28,T60 

 LINE       188
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_aon)
             ----------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T28,T60 

 LINE       201
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_i)
             ----------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T28,T60 

 LINE       203
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_i)
             ----------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T28,T60
Branch Coverage for Module : usbdev_aon_wake
Line No.TotalCoveredPercent
Branches 19 18 94.74
TERNARY 186 2 2 100.00
TERNARY 188 2 2 100.00
TERNARY 201 2 2 100.00
TERNARY 203 2 2 100.00
IF 123 2 2 100.00
CASE 139 5 4 80.00
IF 163 2 2 100.00
IF 192 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	186	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Covered T1,T28,T60
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	188	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Covered T1,T28,T60
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	201	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Covered T1,T28,T60
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	203	(wake_detect_active_q) ?

Branches:
-1-StatusTests
1 Covered T1,T28,T60
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	123	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	139	case (wake_detect_active_q)
-2-:	142	if (suspend_req_aon_i)
-3-:	151	if (wake_ack_aon_i)

Branches:
-1--2--3-StatusTests
1'b0 1 - Covered T1,T28,T60
1'b0 0 - Covered T1,T28,T60
1'b1 - 1 Covered T1,T60,T13
1'b1 - 0 Covered T1,T28,T60
default - - Not Covered 



	LineNo.	Expression
-1-:	163	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	192	if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Module : usbdev_aon_wake
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WakeDetectActiveAonKnown_A 1620407 1427002 0 0


WakeDetectActiveAonKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1620407 1427002 0 0
T4 668 494 0 0
T5 807 634 0 0
T6 412 179 0 0
T15 1091 918 0 0
T16 804 630 0 0
T61 590 416 0 0
T88 525 352 0 0
T89 471 299 0 0
T90 1208 1145 0 0
T91 370 197 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%