Unified Coverage Report :: Module

Module : rv_plic_target

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.63	89.34	77.18			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.30	99.83	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_max_tree	91.60	89.27	77.15			100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	62	5	5	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
59	1	1
62	1	1
63	1	1
64	1	1
66	1	1
67	1	1
71	1	1
72	1	1

Cond Coverage for Module : rv_plic_target

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((max_value > threshold_i) ? max_valid : 1'b0)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T16

 LINE       59
 EXPRESSION (max_valid ? max_idx : '0)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T16

Branch Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	58	2	2	100.00
TERNARY	59	2	2	100.00
IF	62	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	58	((max_value > threshold_i)) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	59	(max_valid) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6