Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1854309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38226150

1

T4

5507

T5

3706

T6

8123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28001214	1			T4	2101		T5	1013		T6	2529
values[0x0]	10668378	1			T4	3406		T5	2693		T6	5594
values[0x1]	1410867	1			T4	230		T5	151		T6	383

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	606018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39474441

1

T4

5737

T5

3857

T6

8506

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18840174	1			T4	2869		T5	1929		T6	4253
valid_sources[0x01]	18839491	1			T4	2868		T5	1928		T6	4253
valid_sources[0x02]	40382	1			T197	1		T78	99		T81	6
valid_sources[0x03]	37709	1			T196	1		T78	134		T81	17
valid_sources[0x04]	38639	1			T78	124		T81	13		T375	392
valid_sources[0x05]	38304	1			T197	1		T78	165		T81	13
valid_sources[0x06]	37596	1			T196	1		T78	67		T81	17
valid_sources[0x07]	39280	1			T58	2		T78	183		T81	12
valid_sources[0x08]	38847	1			T197	2		T78	220		T81	14
valid_sources[0x09]	38722	1			T58	2		T78	144		T81	16
valid_sources[0x0a]	38362	1			T196	1		T78	147		T81	13
valid_sources[0x0b]	37231	1			T196	1		T78	190		T81	10
valid_sources[0x0c]	40447	1			T58	2		T197	1		T78	172
valid_sources[0x0d]	37561	1			T78	216		T81	14		T375	431
valid_sources[0x0e]	38659	1			T196	3		T78	98		T81	16
valid_sources[0x0f]	37456	1			T78	118		T81	11		T375	367
valid_sources[0x10]	38164	1			T196	1		T197	1		T198	39
valid_sources[0x11]	39239	1			T58	1		T78	113		T81	9
valid_sources[0x12]	38527	1			T197	1		T78	107		T81	9
valid_sources[0x13]	38920	1			T196	2		T78	135		T81	22
valid_sources[0x14]	38700	1			T58	2		T196	3		T78	128
valid_sources[0x15]	40668	1			T58	4		T78	148		T81	11
valid_sources[0x16]	39887	1			T58	1		T78	96		T81	16
valid_sources[0x17]	37861	1			T197	1		T78	194		T81	18
valid_sources[0x18]	38230	1			T197	1		T78	144		T81	18
valid_sources[0x19]	38114	1			T196	2		T78	96		T81	12
valid_sources[0x1a]	39100	1			T197	3		T78	143		T81	8
valid_sources[0x1b]	38360	1			T58	1		T196	1		T197	1
valid_sources[0x1c]	40415	1			T78	126		T81	17		T375	375
valid_sources[0x1d]	38531	1			T196	4		T197	2		T78	217
valid_sources[0x1e]	38911	1			T196	1		T78	152		T81	11
valid_sources[0x1f]	38003	1			T78	100		T81	9		T375	401
valid_sources[0x20]	38739	1			T196	6		T197	1		T78	190

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27321386

1

T4

2101

T5

1013

T6

2529

values[0x0]

all_enables

biggest_size

10625864

1

T4

3406

T5

2693

T6

5594

values[0x1]

all_enables

biggest_size

278900

1

T58

19

T79

18

T80

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2761978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

435816

1

T76

302

T77

285

T82

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1083548	1			T76	767		T77	685		T82	45
values[0x0]	1033660	1			T76	768		T77	645		T82	50
values[0x1]	1080586	1			T76	720		T77	622		T82	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2138945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1058849

1

T76

731

T77

664

T82

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48706	1			T76	40		T77	25		T82	1
valid_sources[0x01]	49407	1			T76	4		T77	29		T82	2
valid_sources[0x02]	50414	1			T76	22		T77	36		T82	1
valid_sources[0x03]	50029	1			T76	28		T77	36		T82	2
valid_sources[0x04]	49452	1			T76	25		T77	28		T82	2
valid_sources[0x05]	49751	1			T76	71		T77	30		T82	5
valid_sources[0x06]	50160	1			T76	26		T77	28		T82	2
valid_sources[0x07]	49142	1			T76	36		T77	29		T82	4
valid_sources[0x08]	49200	1			T76	10		T77	32		T150	53
valid_sources[0x09]	50388	1			T76	36		T77	23		T82	2
valid_sources[0x0a]	49747	1			T76	26		T77	34		T82	1
valid_sources[0x0b]	49417	1			T76	51		T77	26		T150	32
valid_sources[0x0c]	49602	1			T76	45		T77	34		T82	2
valid_sources[0x0d]	48931	1			T76	45		T77	48		T82	4
valid_sources[0x0e]	49449	1			T76	49		T77	35		T82	3
valid_sources[0x0f]	49517	1			T76	39		T77	41		T82	4
valid_sources[0x10]	50289	1			T76	18		T77	37		T82	5
valid_sources[0x11]	49733	1			T76	59		T77	32		T150	44
valid_sources[0x12]	49539	1			T76	65		T77	45		T82	2
valid_sources[0x13]	49653	1			T76	43		T77	39		T82	2
valid_sources[0x14]	49877	1			T76	28		T77	28		T82	1
valid_sources[0x15]	49622	1			T76	20		T77	30		T150	37
valid_sources[0x16]	50292	1			T76	66		T77	33		T82	4
valid_sources[0x17]	49518	1			T76	25		T77	24		T82	2
valid_sources[0x18]	49659	1			T76	8		T77	31		T82	2
valid_sources[0x19]	49814	1			T76	35		T77	31		T82	7
valid_sources[0x1a]	50585	1			T76	43		T77	22		T82	4
valid_sources[0x1b]	50942	1			T76	59		T77	29		T82	3
valid_sources[0x1c]	49839	1			T76	36		T77	33		T82	4
valid_sources[0x1d]	49067	1			T76	24		T77	26		T82	2
valid_sources[0x1e]	49432	1			T76	34		T77	27		T150	46
valid_sources[0x1f]	50382	1			T76	11		T77	34		T82	4
valid_sources[0x20]	50006	1			T76	42		T77	22		T82	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45798

1

T76

34

T77

31

T82

2

values[0x0]

all_enables

biggest_size

344374

1

T76

245

T77

230

T82

18

values[0x1]

all_enables

biggest_size

45644

1

T76

23

T77

24

T82

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2932945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

476970

1

T76

312

T77

281

T82

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1166624	1			T76	766		T77	709		T82	40
values[0x0]	1075445	1			T76	705		T77	675		T82	46
values[0x1]	1167846	1			T76	761		T77	720		T82	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2249011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1160904

1

T76

750

T77

684

T82

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52350	1			T76	21		T77	30		T82	4
valid_sources[0x01]	52265	1			T76	32		T77	78		T82	2
valid_sources[0x02]	52615	1			T76	29		T77	24		T150	29
valid_sources[0x03]	53303	1			T76	47		T77	31		T82	4
valid_sources[0x04]	52650	1			T76	26		T77	17		T82	4
valid_sources[0x05]	53378	1			T76	35		T77	40		T82	1
valid_sources[0x06]	52931	1			T76	26		T77	32		T82	1
valid_sources[0x07]	52806	1			T76	46		T77	46		T82	3
valid_sources[0x08]	53854	1			T76	40		T77	25		T82	1
valid_sources[0x09]	53229	1			T76	33		T77	28		T82	3
valid_sources[0x0a]	53637	1			T76	40		T77	25		T150	34
valid_sources[0x0b]	54431	1			T76	25		T77	40		T150	44
valid_sources[0x0c]	52742	1			T76	34		T77	46		T82	2
valid_sources[0x0d]	52784	1			T76	32		T77	20		T82	5
valid_sources[0x0e]	52109	1			T76	35		T77	33		T82	1
valid_sources[0x0f]	52923	1			T76	41		T77	27		T150	51
valid_sources[0x10]	53631	1			T76	34		T77	22		T150	44
valid_sources[0x11]	52523	1			T76	27		T77	55		T150	47
valid_sources[0x12]	52820	1			T76	46		T77	54		T82	4
valid_sources[0x13]	53099	1			T76	23		T77	59		T82	1
valid_sources[0x14]	54170	1			T76	33		T77	42		T82	2
valid_sources[0x15]	53040	1			T76	46		T77	28		T82	2
valid_sources[0x16]	54861	1			T76	37		T77	32		T150	40
valid_sources[0x17]	53720	1			T76	41		T77	25		T82	1
valid_sources[0x18]	52972	1			T76	35		T77	41		T82	2
valid_sources[0x19]	52535	1			T76	34		T77	35		T82	5
valid_sources[0x1a]	52946	1			T76	31		T77	34		T82	1
valid_sources[0x1b]	53222	1			T76	37		T77	49		T150	52
valid_sources[0x1c]	53774	1			T76	41		T77	34		T82	1
valid_sources[0x1d]	53785	1			T76	33		T77	12		T82	6
valid_sources[0x1e]	53215	1			T76	33		T77	40		T82	3
valid_sources[0x1f]	53497	1			T76	37		T77	42		T82	1
valid_sources[0x20]	53000	1			T76	33		T77	36		T150	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50217

1

T76

35

T77

26

T82

2

values[0x0]

all_enables

biggest_size

376973

1

T76

246

T77

231

T82

14

values[0x1]

all_enables

biggest_size

49780

1

T76

31

T77

24

T82

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2783666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

440168

1

T76

340

T77

250

T82

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1091002	1			T76	823		T77	624		T82	34
values[0x0]	1042120	1			T76	799		T77	579		T82	39
values[0x1]	1090712	1			T76	801		T77	619		T82	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2155778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1068056

1

T76

860

T77

592

T82

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49227	1			T76	33		T77	47		T82	2
valid_sources[0x01]	50173	1			T76	36		T77	25		T82	1
valid_sources[0x02]	50643	1			T76	43		T77	30		T82	5
valid_sources[0x03]	50170	1			T76	37		T77	18		T150	57
valid_sources[0x04]	50159	1			T76	37		T77	36		T82	4
valid_sources[0x05]	50160	1			T76	55		T77	25		T150	48
valid_sources[0x06]	49747	1			T76	48		T150	50		T250	5
valid_sources[0x07]	49777	1			T76	41		T77	13		T82	1
valid_sources[0x08]	50257	1			T76	33		T77	17		T82	3
valid_sources[0x09]	50919	1			T76	37		T77	25		T82	3
valid_sources[0x0a]	50287	1			T76	42		T77	38		T82	2
valid_sources[0x0b]	49870	1			T76	32		T77	51		T150	50
valid_sources[0x0c]	49014	1			T76	33		T77	17		T150	42
valid_sources[0x0d]	50011	1			T76	48		T77	17		T82	1
valid_sources[0x0e]	49460	1			T76	29		T77	14		T82	2
valid_sources[0x0f]	50568	1			T76	29		T77	8		T150	52
valid_sources[0x10]	51455	1			T76	45		T77	16		T150	51
valid_sources[0x11]	50433	1			T76	35		T77	44		T82	1
valid_sources[0x12]	50407	1			T76	35		T150	47		T126	14
valid_sources[0x13]	50949	1			T76	36		T77	38		T150	52
valid_sources[0x14]	50372	1			T76	32		T77	54		T82	4
valid_sources[0x15]	51173	1			T76	26		T77	40		T82	5
valid_sources[0x16]	49769	1			T76	33		T77	51		T150	39
valid_sources[0x17]	49872	1			T76	48		T77	31		T82	3
valid_sources[0x18]	50913	1			T76	46		T77	24		T82	4
valid_sources[0x19]	50093	1			T76	42		T77	28		T150	47
valid_sources[0x1a]	50844	1			T76	35		T77	28		T82	1
valid_sources[0x1b]	49846	1			T76	33		T77	43		T82	4
valid_sources[0x1c]	50094	1			T76	36		T77	15		T82	3
valid_sources[0x1d]	49987	1			T76	46		T77	29		T150	47
valid_sources[0x1e]	50023	1			T76	42		T77	66		T150	51
valid_sources[0x1f]	51821	1			T76	35		T77	106		T150	59
valid_sources[0x20]	49816	1			T76	54		T77	2		T82	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46059

1

T76

27

T77

22

T82

3

values[0x0]

all_enables

biggest_size

348039

1

T76

282

T77

193

T82

14

values[0x1]

all_enables

biggest_size

46070

1

T76

31

T77

35

T82

3