Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	86	86	100.00
Total Bits	938	938	100.00
Total Bits 0->1	469	469	100.00
Total Bits 1->0	469	469	100.00

Ports	86	86	100.00
Port Bits	938	938	100.00
Port Bits 0->1	469	469	100.00
Port Bits 1->0	469	469	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_lc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T15,T17	Yes	T4,T5,T6	INPUT
rst_lc_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T6,T15,T17	Yes	T4,T5,T6	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T41,T7,T304	Yes	T41,T7,T304	OUTPUT
dmactive_o	Yes	Yes	T57,T58,T70	Yes	T41,T56,T57	OUTPUT
debug_req_o	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_address[3:0]	Yes	Yes	T76,T77,T150	Yes	T76,T77,T150	INPUT
regs_tl_d_i.a_address[20:4]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T76,T78,T81	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
regs_tl_d_o.d_source[5:0]	Yes	Yes	T76,T77,T150	Yes	T76,T77,T82	OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_address[11:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T41,*T56,*T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[5:0]	Yes	Yes	*T41,*T56,*T255	Yes	T41,T56,T255	INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	OUTPUT
mem_tl_d_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
mem_tl_d_o.d_source[5:0]	Yes	Yes	*T41,*T56,*T255	Yes	T41,T56,T255	OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T6,T41,T15	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
sba_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
sba_tl_h_o.a_address[31:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
sba_tl_h_o.a_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[2:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
sba_tl_h_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
sba_tl_h_i.d_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T41,*T56,*T57	Yes	T41,T56,T57	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T347,T84,T85	Yes	T347,T84,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T347,T84,T85	Yes	T347,T84,T85	OUTPUT
jtag_i.tdi	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
jtag_i.trst_n	Yes	Yes	T57,T58,T70	Yes	T41,T56,T57	INPUT
jtag_i.tms	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
jtag_i.tck	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
jtag_o.tdo_oe	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
jtag_o.tdo	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT

*Tests covering at least one bit in the range