Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : ibex_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.58 93.58

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core 95.91 95.91



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.91 95.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.91 95.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ibex_top
TotalCoveredPercent
Totals 42 33 78.57
Total Bits 826 773 93.58
Total Bits 0->1 413 387 93.70
Total Bits 1->0 413 386 93.46

Ports 42 33 78.57
Port Bits 826 773 93.58
Port Bits 0->1 413 387 93.70
Port Bits 1->0 413 386 93.46

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T41,T15 Yes T4,T5,T6 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
instr_gnt_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_rvalid_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
instr_addr_o[18:17] No No No OUTPUT
instr_addr_o[19] No No Yes T385,T303,T386 OUTPUT
instr_addr_o[27:20] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T103,*T56,*T269 Yes T103,T56,T269 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_rdata_intg_i[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_err_i Yes Yes T41,T219,T160 Yes T41,T219,T160 INPUT
data_req_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_gnt_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_rvalid_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_we_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_be_o[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_wdata_o[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_rdata_i[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_rdata_intg_i[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_err_i Yes Yes T41,T66,T190 Yes T41,T66,T190 INPUT
irq_software_i Yes Yes T252,T79,T80 Yes T252,T79,T80 INPUT
irq_timer_i Yes Yes T253,T151,T254 Yes T253,T151,T254 INPUT
irq_external_i Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T15,T17,T168 Yes T15,T17,T168 INPUT
scramble_key_valid_i Yes Yes T176,T177,T178 Yes T176,T177,T178 INPUT
scramble_key_i[127:0] Yes Yes T4,T6,T41 Yes T6,T41,T17 INPUT
scramble_nonce_i[63:0] Yes Yes T5,T6,T41 Yes T4,T5,T6 INPUT
scramble_req_o Yes Yes T174,T175,T176 Yes T174,T175,T176 OUTPUT
debug_req_i Yes Yes T41,T56,T255 Yes T41,T56,T255 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T92,T243,T244 Yes T92,T243,T244 OUTPUT
fetch_enable_i[3:0] Yes Yes T6,T41,T15 Yes T4,T5,T6 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T387 Yes T387 OUTPUT
alert_major_bus_o Yes Yes T103,T171,T242 Yes T103,T171,T242 OUTPUT
core_sleep_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core
TotalCoveredPercent
Totals 38 33 86.84
Total Bits 806 773 95.91
Total Bits 0->1 403 387 96.03
Total Bits 1->0 403 386 95.78

Ports 38 33 86.84
Port Bits 806 773 95.91
Port Bits 0->1 403 387 96.03
Port Bits 1->0 403 386 95.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T41,T15 Yes T4,T5,T6 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
instr_gnt_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_rvalid_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
instr_addr_o[18:17] No No No OUTPUT
instr_addr_o[19] No No Yes T385,T303,T386 OUTPUT
instr_addr_o[27:20] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T103,*T56,*T269 Yes T103,T56,T269 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_rdata_intg_i[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
instr_err_i Yes Yes T41,T219,T160 Yes T41,T219,T160 INPUT
data_req_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_gnt_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_rvalid_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_we_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_be_o[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_wdata_o[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_rdata_i[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_rdata_intg_i[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_err_i Yes Yes T41,T66,T190 Yes T41,T66,T190 INPUT
irq_software_i Yes Yes T252,T79,T80 Yes T252,T79,T80 INPUT
irq_timer_i Yes Yes T253,T151,T254 Yes T253,T151,T254 INPUT
irq_external_i Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T15,T17,T168 Yes T15,T17,T168 INPUT
scramble_key_valid_i Yes Yes T176,T177,T178 Yes T176,T177,T178 INPUT
scramble_key_i[127:0] Yes Yes T4,T6,T41 Yes T6,T41,T17 INPUT
scramble_nonce_i[63:0] Yes Yes T5,T6,T41 Yes T4,T5,T6 INPUT
scramble_req_o Yes Yes T174,T175,T176 Yes T174,T175,T176 OUTPUT
debug_req_i Yes Yes T41,T56,T255 Yes T41,T56,T255 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T92,T243,T244 Yes T92,T243,T244 OUTPUT
fetch_enable_i[3:0] Yes Yes T6,T41,T15 Yes T4,T5,T6 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T387 Yes T387 OUTPUT
alert_major_bus_o Yes Yes T103,T171,T242 Yes T103,T171,T242 OUTPUT
core_sleep_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%