Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517005398	59654103	0	0
DepthKnown_A	517005398	516897784	0	0
RvalidKnown_A	517005398	516897784	0	0
WreadyKnown_A	517005398	516897784	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	59654103	0	0
T4	83781	8396	0	0
T5	77807	8614	0	0
T6	179664	15082	0	0
T15	242013	31562	0	0
T16	143564	19362	0	0
T17	240626	31701	0	0
T18	224235	22921	0	0
T41	143211	38652	0	0
T60	100934	16258	0	0
T73	889741	3461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517005398	45836999	0	0
DepthKnown_A	517005398	516897784	0	0
RvalidKnown_A	517005398	516897784	0	0
WreadyKnown_A	517005398	516897784	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	45836999	0	0
T4	83781	6494	0	0
T5	77807	6238	0	0
T6	179664	11317	0	0
T15	242013	22057	0	0
T16	143564	14233	0	0
T17	240626	22020	0	0
T18	224235	17236	0	0
T41	143211	18394	0	0
T60	100934	10690	0	0
T73	889741	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517005398	44335928	0	0
DepthKnown_A	517005398	516897784	0	0
RvalidKnown_A	517005398	516897784	0	0
WreadyKnown_A	517005398	516897784	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	44335928	0	0
T4	83781	5859	0	0
T5	77807	4003	0	0
T6	179664	8749	0	0
T15	242013	15691	0	0
T16	143564	8249	0	0
T17	240626	15586	0	0
T18	224235	13475	0	0
T41	143211	12776	0	0
T60	100934	6573	0	0
T73	889741	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517005398	37721491	0	0
DepthKnown_A	517005398	516897784	0	0
RvalidKnown_A	517005398	516897784	0	0
WreadyKnown_A	517005398	516897784	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	37721491	0	0
T4	83781	5737	0	0
T5	77807	3857	0	0
T6	179664	8506	0	0
T15	242013	15314	0	0
T16	143564	7971	0	0
T17	240626	15200	0	0
T18	224235	13066	0	0
T41	143211	7950	0	0
T60	100934	6381	0	0
T73	889741	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517005398	516897784	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	100629	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	100629	0	0
T4	83781	13	0	0
T5	77807	13	0	0
T6	179664	28	0	0
T15	242013	151	0	0
T16	143564	26	0	0
T17	240626	151	0	0
T18	224235	49	0	0
T41	143211	26	0	0
T60	100934	17	0	0
T73	889741	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	104506	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	104506	0	0
T4	83781	13	0	0
T5	77807	13	0	0
T6	179664	28	0	0
T15	242013	151	0	0
T16	143564	26	0	0
T17	240626	151	0	0
T18	224235	49	0	0
T41	143211	26	0	0
T60	100934	17	0	0
T73	889741	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	52220	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	52220	0	0
T4	83781	12	0	0
T5	77807	12	0	0
T6	179664	26	0	0
T15	242013	95	0	0
T16	143564	23	0	0
T17	240626	95	0	0
T18	224235	46	0	0
T41	143211	24	0	0
T60	100934	12	0	0
T73	889741	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	52220	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	52220	0	0
T4	83781	12	0	0
T5	77807	12	0	0
T6	179664	26	0	0
T15	242013	95	0	0
T16	143564	23	0	0
T17	240626	95	0	0
T18	224235	46	0	0
T41	143211	24	0	0
T60	100934	12	0	0
T73	889741	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	48409	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	48409	0	0
T4	83781	1	0	0
T5	77807	1	0	0
T6	179664	2	0	0
T15	242013	56	0	0
T16	143564	3	0	0
T17	240626	56	0	0
T18	224235	3	0	0
T41	143211	2	0	0
T60	100934	5	0	0
T73	889741	0	0	0
T192	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	603844872	52286	0	0
DepthKnown_A	603844872	603725054	0	0
RvalidKnown_A	603844872	603725054	0	0
WreadyKnown_A	603844872	603725054	0	0
gen_passthru_fifo.paramCheckPass	2911	2911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	52286	0	0
T4	83781	1	0	0
T5	77807	1	0	0
T6	179664	2	0	0
T15	242013	56	0	0
T16	143564	3	0	0
T17	240626	56	0	0
T18	224235	3	0	0
T41	143211	2	0	0
T60	100934	5	0	0
T73	889741	0	0	0
T192	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603844872	603725054	0	0
T4	83781	83723	0	0
T5	77807	77749	0	0
T6	179664	179511	0	0
T15	242013	241889	0	0
T16	143564	143513	0	0
T17	240626	240509	0	0
T18	224235	224064	0	0
T41	143211	143098	0	0
T60	100934	100872	0	0
T73	889741	889679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2911	2911	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T41	1	1	0	0
T60	1	1	0	0
T73	1	1	0	0