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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_8


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_9


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_10


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_11


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_12


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_15


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_16


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_17


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T428,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT375,T143,T376
10CoveredT428,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T428,T375
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T429,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT375,T143,T376
10CoveredT375,T143,T376
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T429,T375
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T536,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T536,T375
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T536,T375
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT375,T143,T144
10CoveredT375,T143,T144
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT375,T143,T144
10CoveredT375,T143,T144
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T429,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T429,T375
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T428,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT375,T143,T144
10CoveredT375,T143,T144
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T428,T375
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T375,T143 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T375,T143
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T375,T143
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT78,T429,T375 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT78,T375,T143
10CoveredT78,T429,T375
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT78,T429,T375
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%