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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 100.00 95.92 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.69 97.14 97.62 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.25 99.77 97.24 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.91 97.37 78.26 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.30 94.29 76.54 86.36 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.95 100.00 71.82 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 83.23 96.15 74.29 62.50 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.46 100.00 97.83 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 97.14 98.77 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.98 100.00 99.90 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.91 100.00 95.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 97.14 97.53 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.92 100.00 99.68 100.00 100.00 u_reg_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
TotalCoveredPercent
Conditions494795.92
Logical494795.92
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT56,T52,T179
11CoveredT4,T5,T6

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT58,T79,T80
10CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT58,T79,T80

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT76,T77,T81
11CoveredT4,T5,T6

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT250,T450,T451
11CoveredT4,T5,T6

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT4,T5,T6
010CoveredT697
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT81,T546,T550
10CoveredT81,T546,T550

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10CoveredT4,T5,T6

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01CoveredT144,T411,T530
10CoveredT4,T5,T6
11CoveredT1,T2,T3

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT4,T5,T6
00001Unreachable
00010CoveredT696,T698,T699
00100CoveredT4,T5,T6
01000Not Covered
10000CoveredT76,T77,T82

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T6
0 0 1 Covered T4,T5,T6
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T6
0 1 0 Covered T4,T5,T6
0 0 - Covered T4,T5,T6


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T6
0 1 0 Covered T4,T5,T6
0 0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2911 2911 0 0
MatchedWidthAssert 2911 2911 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL383797.37
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 0 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
TotalCoveredPercent
Conditions463678.26
Logical463678.26
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT112,T38,T39
11CoveredT4,T5,T6

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT60,T122,T61

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT58,T79,T80
10CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT58,T79,T80

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT60,T122,T61
11CoveredT4,T5,T6

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT60,T122,T61

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT60,T122,T61
10Not Covered
11CoveredT4,T5,T6

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT60,T122,T61
1CoveredT4,T5,T6

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT60,T122,T61

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT60,T122,T61
010Not Covered
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10Not Covered

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT4,T5,T6

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT4,T5,T6
00001Unreachable
00010Not Covered
00100CoveredT4,T5,T6
01000Not Covered
10000Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T6
0 0 1 Covered T4,T5,T6
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T6
0 1 0 Covered T60,T122,T61
0 0 - Covered T4,T5,T6


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T60,T122,T61
0 Covered T60,T122,T61


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T60,T122,T61
0 1 0 Covered T4,T5,T6
0 0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 1021 1021 0 0
MatchedWidthAssert 1021 1021 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1021 1021 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 1021 1021 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
TotalCoveredPercent
Conditions464597.83
Logical464597.83
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT376,T395,T397
11CoveredT60,T15,T16

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT376,T395,T397
11CoveredT60,T15,T16

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT15,T16,T17
11CoveredT60,T15,T16

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT15,T16,T17
01CoveredT76,T77,T78
10CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT15,T16,T17
1CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT76,T77,T78

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT376,T395,T397
10CoveredT60,T15,T16
11CoveredT15,T16,T17

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT15,T16,T17

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT15,T16,T17
10CoveredT76,T77,T81
11CoveredT60,T15,T16

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT60,T15,T16
10CoveredT81,T250,T450
11CoveredT15,T16,T17

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT60,T15,T16
1CoveredT15,T16,T17

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT15,T16,T17
1CoveredT60,T15,T16

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT15,T16,T17
001CoveredT60,T15,T16
010CoveredT81,T546,T550
100CoveredT695

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT60,T15,T16
01CoveredT81,T546,T550
10CoveredT81,T546,T550

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT60,T15,T16

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT60,T15,T16
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT60,T15,T16
00001Unreachable
00010CoveredT700,T699,T701
00100CoveredT81,T250,T450
01000Not Covered
10000CoveredT76,T77,T82

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T60,T15,T16
0 0 1 Covered T60,T15,T16
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T15,T16,T17
0 1 0 Covered T60,T15,T16
0 0 - Covered T4,T5,T6


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T60,T15,T16
0 Covered T60,T15,T16


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T60,T15,T16
0 1 0 Covered T15,T16,T17
0 0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2911 2911 0 0
MatchedWidthAssert 2911 2911 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT376,T395,T396
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT376,T395,T397
11CoveredT4,T5,T6

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT60,T15,T17

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT76,T77,T78
10CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT76,T77,T78

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT76,T77,T430
10CoveredT60,T15,T17
11CoveredT4,T5,T6

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT76,T77,T81
11CoveredT60,T15,T17

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT60,T15,T17
10CoveredT250,T450,T451
11CoveredT4,T5,T6

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT60,T15,T17
1CoveredT4,T5,T6

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT60,T15,T17

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT60,T15,T17
010CoveredT81,T546,T544
100Not Covered

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT81,T546,T550
10CoveredT81,T546,T550

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT4,T5,T6

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT4,T5,T6
00001Unreachable
00010CoveredT450,T451,T702
00100CoveredT4,T5,T6
01000Not Covered
10000CoveredT76,T77,T126

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T6
0 0 1 Covered T4,T5,T6
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T4,T5,T6
0 1 0 Covered T60,T15,T17
0 0 - Covered T4,T5,T6


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T60,T15,T17
0 Covered T4,T5,T6


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 1 Covered T60,T15,T17
0 1 0 Covered T4,T5,T6
0 0 - Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 2911 2911 0 0
MatchedWidthAssert 2911 2911 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2911 2911 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T41 1 1 0 0
T60 1 1 0 0
T73 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%