Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	50	50	100.00
Total Bits	334	334	100.00
Total Bits 0->1	167	167	100.00
Total Bits 1->0	167	167	100.00

Ports	50	50	100.00
Port Bits	334	334	100.00
Port Bits 0->1	167	167	100.00
Port Bits 1->0	167	167	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T66,T203	Yes	T18,T66,T203	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T66,T203	Yes	T18,T66,T203	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[7:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T41,*T56,*T57	Yes	T41,T56,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T79,T80	Yes	T58,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T60,T18,T66	Yes	T60,T18,T66	INPUT
tl_o.a_ready	Yes	Yes	T60,T18,T66	Yes	T60,T18,T66	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T66,T203	Yes	T18,T66,T203	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T66,T203	Yes	T60,T18,T66	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T66,T203	Yes	T60,T18,T66	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T66,*T203	Yes	T18,T66,T203	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T18,T66	Yes	T60,T18,T66	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T15,T61	Yes	T60,T15,T61	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T15,T61	Yes	T60,T15,T61	OUTPUT
wkup_req_o	Yes	Yes	T18,T66,T3	Yes	T18,T66,T203	OUTPUT
rst_req_o	Yes	Yes	T18,T66,T30	Yes	T18,T66,T30	OUTPUT
intr_event_detected_o	Yes	Yes	T203,T309,T207	Yes	T203,T309,T207	OUTPUT
cio_ac_present_i	Yes	Yes	T203,T30,T204	Yes	T203,T30,T204	INPUT
cio_ec_rst_l_i	Yes	Yes	T203,T30,T204	Yes	T203,T30,T8	INPUT
cio_key0_in_i	Yes	Yes	T18,T66,T203	Yes	T18,T66,T203	INPUT
cio_key1_in_i	Yes	Yes	T203,T30,T204	Yes	T203,T30,T204	INPUT
cio_key2_in_i	Yes	Yes	T203,T30,T204	Yes	T203,T30,T204	INPUT
cio_pwrb_in_i	Yes	Yes	T203,T3,T30	Yes	T203,T3,T30	INPUT
cio_lid_open_i	Yes	Yes	T30,T204,T46	Yes	T30,T204,T46	INPUT
cio_flash_wp_l_i	Yes	Yes	T203,T30,T31	Yes	T203,T30,T8	INPUT
cio_bat_disable_o	Yes	Yes	T18,T66,T276	Yes	T18,T66,T276	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T30,T31,T32	Yes	T30,T46,T31	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
cio_key0_out_o	Yes	Yes	T18,T66,T203	Yes	T18,T66,T203	OUTPUT
cio_key1_out_o	Yes	Yes	T203,T30,T204	Yes	T203,T30,T204	OUTPUT
cio_key2_out_o	Yes	Yes	T203,T30,T204	Yes	T203,T30,T204	OUTPUT
cio_pwrb_out_o	Yes	Yes	T203,T3,T30	Yes	T203,T3,T30	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T30,T31,T32	Yes	T30,T46,T31	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range