Module Definition
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Module : tlul_err_resp
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.75 95.24 80.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp 91.75 95.24 80.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.75 95.24 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.32 77.27 80.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 80.43 60.87 100.00

Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL212095.24
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN53100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 0 1
55 1 1
58 1 1
59 1 1
65 1 1


Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((err_rsp_pending && tl_h_i.d_ready)) -3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T6
0 0 1 Covered T4,T5,T6
0 0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp
Line No.TotalCoveredPercent
TOTAL212095.24
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN53100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 0 1
55 1 1
58 1 1
59 1 1
65 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp
TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((err_rsp_pending && tl_h_i.d_ready)) -3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T4,T5,T6
0 0 1 Covered T4,T5,T6
0 0 0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%