Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T76,T82,T150	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T82,T250,T251	Yes	T82,T250,T251	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T41,T219,T160	Yes	T41,T219,T160	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T41,T103,T219	Yes	T41,T103,T219	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T58,T79,T80	Yes	T58,T79,T80	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T79,T81,T150	Yes	T79,T81,T150	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T41,T66,T190	Yes	T41,T66,T190	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T41,*T56,*T57	Yes	T41,T56,T57	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T41,T56,T57	Yes	T41,T56,T57	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T76,T78,T81	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T76,T77,T150	Yes	T76,T77,T82	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T41,*T56,*T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T41,*T56,*T255	Yes	T41,T56,T255	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T6,T41,T15	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T41,T56,T255	Yes	T41,T56,T255	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T73,T55,T52	Yes	T73,T55,T52	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T55,T52,T179	Yes	T55,T52,T179	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T81	Yes	T76,T77,T81	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T82	Yes	T76,T77,T82	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T265,T266,T405	Yes	T265,T266,T405	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T60,T61,T62	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T265,T266,T405	Yes	T60,T61,T265	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T76,T77,*T126	Yes	T76,T77,T82	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T404,*T265,*T266	Yes	T404,T265,T266	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T60,T61,T404	Yes	T60,T61,T404	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T41,*T56,*T57	Yes	T41,T56,T57	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T58,T79,T80	Yes	T58,T79,T80	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T190,T103,T219	Yes	T190,T103,T219	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T41,*T56,*T57	Yes	T41,T56,T57	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T25,T26,T193	Yes	T25,T26,T193	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T24,T209,T25	Yes	T24,T209,T25	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T24,T247,T209	Yes	T60,T61,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T24,T209,T25	Yes	T24,T209,T25	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T76,T77,T150	Yes	T76,T77,T150	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T24,*T247,*T209	Yes	T24,T247,T209	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T60,T61,T24	Yes	T60,T61,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T209	Yes	T60,T61,T209	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T60,T61,T209	Yes	T60,T61,T209	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T209,T151,T393	Yes	T209,T151,T393	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T247,T209,T151	Yes	T60,T61,T247	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T209,T151,T393	Yes	T209,T151,T393	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T247,*T209,*T151	Yes	T247,T209,T151	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T60,T61,T247	Yes	T60,T61,T247	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	INPUT
tl_usbdev_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T27,T247,T309	Yes	T27,T247,T309	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T247,T309	Yes	T27,T247,T309	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T60,T27,T61	Yes	T27,T28,T29	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T60,*T27,*T61	Yes	T27,T28,T29	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T60,T27,T61	Yes	T60,T27,T61	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T197,T76,T78	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T197,T76,T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T197,T76,T77	Yes	T197,T76,T77	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T6,T60	Yes	T4,T6,T60	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T81	Yes	T76,T77,T81	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T268	Yes	T60,T61,T268	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T268	Yes	T60,T61,T268	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T60,T61,T268	Yes	T60,T61,T268	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T268,T402,T314	Yes	T268,T402,T314	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	INPUT
tl_hmac_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T245,T268,T55	Yes	T245,T268,T55	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T268,T55	Yes	T245,T268,T55	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T60,T61,T268	Yes	T268,T55,T402	INPUT
tl_hmac_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T82	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T60,*T61,*T268	Yes	T268,T55,T402	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	INPUT
tl_kmac_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T104,T222,T279	Yes	T104,T222,T279	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	INPUT
tl_kmac_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T149,T104,T105	Yes	T149,T104,T105	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T104,T105	Yes	T149,T104,T105	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T60,T149,T61	Yes	T149,T104,T105	INPUT
tl_kmac_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T60,*T149,*T61	Yes	T104,T105,T19	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T82	Yes	T76,T77,T82	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	INPUT
tl_aes_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T5,T109,T245	Yes	T5,T109,T245	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T109,T96	Yes	T5,T60,T61	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T5,T109,T245	Yes	T5,T60,T61	INPUT
tl_aes_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T82	Yes	T76,T77,T82	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T5,*T109,*T245	Yes	T5,T109,T245	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T96,T114,T123	Yes	T96,T114,T123	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T126	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T96,*T114,*T123	Yes	T96,T55,T114	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T114	Yes	T96,T97,T114	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T114	Yes	T96,T97,T114	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T96,T114,T123	Yes	T96,T114,T123	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T6,T41,T15	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T96,*T114,*T123	Yes	T96,T114,T123	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	INPUT
tl_edn1_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T96,T114,T123	Yes	T96,T114,T123	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T114,T123	Yes	T60,T61,T96	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T96,T114,T123	Yes	T60,T61,T96	INPUT
tl_edn1_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T96,*T114,*T123	Yes	T96,T114,T123	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T60,T15,T16	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T60,T15,T16	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T79,T80,T76	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T60,T15,T16	Yes	T60,T15,T16	INPUT
tl_otbn_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T58,*T196,*T198	Yes	T58,T196,T198	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T60,T61,T245	Yes	T60,T61,T245	INPUT
tl_otbn_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T96,T55,T114	Yes	T96,T55,T114	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T55,T114	Yes	T96,T55,T114	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T60,T61,T96	Yes	T96,T55,T114	INPUT
tl_otbn_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T58,*T196,*T198	Yes	T58,T196,T198	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T60,*T61,*T96	Yes	T96,T55,T114	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T60,T61,T96	Yes	T60,T61,T96	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	INPUT
tl_keymgr_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T149,T105,T96	Yes	T149,T105,T96	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T105,T96	Yes	T60,T149,T61	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T149,T105,T96	Yes	T60,T149,T61	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T126	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T197,*T76,*T77	Yes	T197,T76,T77	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T149,*T105,*T96	Yes	T149,T105,T96	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T60,T149,T61	Yes	T60,T149,T61	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T256,*T76,*T77	Yes	T256,T76,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T82	Yes	T256,T76,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T6,T41,T60	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T255,*T79,*T436	Yes	T255,T79,T436	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T174,T175,T79	Yes	T174,T175,T79	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T171,T53	Yes	T60,T61,T55	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T52,T171,T53	Yes	T60,T61,T55	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T76	Yes	T255,T79,T436	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T171,*T174,*T175	Yes	T171,T174,T175	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T60,T61,T55	Yes	T60,T61,T55	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T41,T15	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range