Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T203,T30,T8 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T39,T40,T45 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T30,T46,T31 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T8,T21,T10 |
| 1 | 0 | Covered | T46,T47,T48 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T46,T47,T48 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T48 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T48 |
| 1 | 1 | Covered | T46,T47,T48 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T8,T46,T21 |
| 1 | Covered | T4,T5,T6 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T8,T46,T21 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T8,T46,T21 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T42,T43,T44 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T45 |
| 1 | 1 | Covered | T38,T39,T45 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T1,T2 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T2 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T1,T2 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T49,T50,T51 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T49,T50,T51 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T2 |
| 0 | 1 | Covered | T4,T1,T2 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T211,T87 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T211,T87 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T211,T87 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T211,T87 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T211,T87 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T58,T21,T79 |
| 0 | 1 | Covered | T21,T42,T43 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T24,T25,T26 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T43,T23,T44 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T43,T23,T44 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T43,T23,T44 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T43,T23,T44 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T43,T23,T44 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T42,T43,T44 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T58,T21,T79 |
| 0 | 1 | Covered | T24,T25,T26 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T42,T43,T44 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T43,T22 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T21,T43,T22 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T21,T43,T22 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T43,T22 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T24,T25,T26 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T43,T22 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T24,T25,T26 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T58,T79,T80 |
| 0 | 1 | Covered | T21,T22,T23 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T21,T23,T38 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T23,T38 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T21,T23,T38 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T21,T23,T38 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T23,T38 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T23,T38 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T203,T58,T30 |
| 0 | 1 | Covered | T203,T24,T30 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T43,T22,T44 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T43,T22 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T21,T43,T22 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T21,T43,T22 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T21,T43,T22 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T24,T25,T26 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T43,T22 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T24,T25,T26 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T58,T212,T213 |
| 0 | 1 | Covered | T212,T213,T21 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T23,T38,T39 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T23,T38,T39 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T23,T38,T39 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T23,T38,T39 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T23,T38,T39 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T23,T38,T39 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T42,T43,T44 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T58,T212,T213 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T42,T43,T44 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T203,T87 |
| 0 | 1 | Covered | T4,T203,T87 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T35 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T35 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T35 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T42,T43,T44 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T35 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T42,T43,T44 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T87,T58 |
| 0 | 1 | Covered | T4,T87,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T46 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T46 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T46 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T46 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T46 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T46 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T203,T87 |
| 0 | 1 | Covered | T4,T203,T87 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T35 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T35 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T35 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T35 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T87,T58 |
| 0 | 1 | Covered | T4,T87,T30 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T214 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T214 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T214 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T214 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T87,T58 |
| 0 | 1 | Covered | T4,T87,T214 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T214 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T214 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T214 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T214 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T87,T58 |
| 0 | 1 | Covered | T4,T87,T35 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T35 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T4,T87,T214 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T87,T214 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T4,T87,T214 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T38,T39,T40 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T87,T214 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T38,T39,T40 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1021 |
1021 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1021 |
1021 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T41 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T73 |
1 |
1 |
0 |
0 |