Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3655691	1			T85	2005		T86	1024		T87	15
values[2]	745670	1			T85	586		T86	286		T87	13
values[3]	104038	1			T85	25		T86	18		T87	13
values[4]	56455	1			T86	2		T87	13		T486	292
values[5]	38787	1			T87	13		T486	166		T828	115
values[6]	29521	1			T87	13		T486	117		T828	65
values[7]	23894	1			T87	13		T486	108		T828	40
values[8]	20621	1			T87	13		T486	63		T828	21
values[9]	18495	1			T87	13		T486	39		T828	41
values[10]	17067	1			T87	13		T486	23		T828	56
values[11]	15471	1			T87	13		T486	15		T828	70
values[12]	14697	1			T87	13		T486	17		T828	65
values[13]	13965	1			T87	13		T486	11		T828	49
values[14]	13223	1			T87	13		T486	11		T828	52
values[15]	13094	1			T87	13		T486	14		T828	37
values[16]	12200	1			T87	13		T486	15		T828	16
values[17]	12097	1			T87	13		T486	9		T828	15
values[18]	11631	1			T87	13		T486	11		T828	14
values[19]	11023	1			T87	13		T486	15		T828	6
values[20]	10809	1			T87	13		T486	12		T828	5
values[21]	10558	1			T87	13		T486	18		T828	3
values[22]	10168	1			T87	13		T486	14		T828	5
values[23]	10064	1			T87	13		T486	14		T828	3
values[24]	9686	1			T87	13		T486	15		T828	4
values[25]	8989	1			T87	13		T486	26		T828	12
values[26]	8657	1			T87	13		T486	19		T828	11
values[27]	8542	1			T87	13		T486	18		T828	9
values[28]	8216	1			T87	13		T486	19		T828	6
values[29]	7458	1			T87	13		T486	15		T828	3
values[30]	6843	1			T87	13		T486	18		T828	6
values[31]	6439	1			T87	13		T486	8		T828	7
values[32]	5976	1			T87	13		T486	9		T828	9
values[33]	5698	1			T87	13		T486	15		T828	10
values[34]	5247	1			T87	13		T486	15		T828	8
values[35]	4893	1			T87	13		T486	14		T828	6
values[36]	4613	1			T87	13		T486	12		T828	5
values[37]	4416	1			T87	13		T486	9		T828	5
values[38]	4131	1			T87	13		T486	16		T828	6
values[39]	4008	1			T87	13		T486	15		T828	7
values[40]	3708	1			T87	13		T486	13		T828	11
values[41]	3640	1			T87	13		T486	14		T828	13
values[42]	3501	1			T87	13		T486	26		T828	8
values[43]	3523	1			T87	13		T486	22		T828	7
values[44]	3288	1			T87	13		T486	22		T828	6
values[45]	3289	1			T87	13		T486	12		T828	8
values[46]	3241	1			T87	13		T486	10		T828	4
values[47]	3135	1			T87	13		T486	13		T828	4
values[48]	3110	1			T87	13		T486	11		T828	5
values[49]	3100	1			T87	13		T486	14		T828	6
values[50]	3044	1			T87	13		T486	9		T828	9
values[51]	3012	1			T87	13		T486	7		T828	8
values[52]	2977	1			T87	13		T486	9		T828	6
values[53]	2907	1			T87	13		T486	8		T828	4
values[54]	2882	1			T87	13		T486	8		T828	6
values[55]	2750	1			T87	13		T486	11		T828	4
values[56]	2721	1			T87	13		T486	11		T828	5
values[57]	2643	1			T87	13		T486	12		T828	11
values[58]	2665	1			T87	13		T486	7		T828	5
values[59]	2590	1			T87	13		T486	7		T828	7
values[60]	2633	1			T87	13		T486	5		T828	5
values[61]	2893	1			T87	14		T486	11		T828	6
values[62]	4373	1			T87	14		T486	32		T828	10
values[63]	11603	1			T87	14		T486	65		T828	64
values[64]	248561	1			T87	2354		T486	290		T828	264

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4720615	1			T85	2051		T86	925		T87	1994
values[2]	812655	1			T85	541		T86	236		T87	589
values[3]	84549	1			T85	62		T86	27		T87	185
values[4]	14752	1			T85	6		T86	2		T87	43
values[5]	5395	1			T87	14		T486	21		T828	1
values[6]	3138	1			T87	6		T486	19		T828	1
values[7]	2375	1			T87	1		T486	17		T828	3
values[8]	2074	1			T87	1		T486	19		T828	1
values[9]	1697	1			T87	1		T486	17		T828	1
values[10]	1664	1			T87	1		T486	21		T828	1
values[11]	1570	1			T87	1		T486	17		T828	3
values[12]	1472	1			T87	1		T486	17		T828	2
values[13]	1369	1			T87	1		T486	30		T828	3
values[14]	1275	1			T87	1		T486	49		T828	4
values[15]	1221	1			T87	1		T486	36		T828	2
values[16]	1144	1			T87	1		T486	14		T828	4
values[17]	1031	1			T87	1		T486	13		T828	2
values[18]	970	1			T87	1		T486	12		T828	1
values[19]	890	1			T87	1		T486	25		T828	2
values[20]	871	1			T87	1		T486	15		T828	3
values[21]	826	1			T87	1		T486	18		T828	4
values[22]	791	1			T87	1		T486	21		T828	1
values[23]	751	1			T87	1		T486	8		T828	1
values[24]	704	1			T87	1		T486	3		T828	1
values[25]	745	1			T87	1		T486	9		T828	1
values[26]	735	1			T87	1		T486	12		T828	1
values[27]	676	1			T87	1		T486	16		T828	2
values[28]	680	1			T87	1		T486	6		T828	1
values[29]	637	1			T87	1		T486	11		T828	1
values[30]	640	1			T87	1		T486	13		T828	1
values[31]	633	1			T87	1		T486	18		T828	1
values[32]	553	1			T87	1		T486	12		T828	1
values[33]	603	1			T87	1		T486	12		T828	1
values[34]	578	1			T87	1		T486	9		T828	1
values[35]	539	1			T87	1		T486	21		T828	1
values[36]	500	1			T87	1		T486	9		T828	1
values[37]	493	1			T87	1		T486	6		T828	4
values[38]	521	1			T87	1		T486	4		T828	3
values[39]	532	1			T87	1		T486	7		T828	3
values[40]	519	1			T87	1		T486	21		T828	1
values[41]	532	1			T87	1		T486	4		T828	2
values[42]	511	1			T87	1		T486	7		T828	2
values[43]	531	1			T87	1		T486	11		T828	2
values[44]	501	1			T87	1		T486	10		T828	2
values[45]	510	1			T87	1		T486	13		T828	2
values[46]	444	1			T87	1		T486	11		T828	1
values[47]	432	1			T87	1		T486	4		T828	1
values[48]	431	1			T87	1		T486	5		T828	1
values[49]	412	1			T87	1		T486	9		T828	1
values[50]	413	1			T87	1		T486	1		T828	2
values[51]	435	1			T87	1		T486	3		T828	2
values[52]	457	1			T87	1		T486	8		T828	1
values[53]	405	1			T87	1		T486	9		T828	1
values[54]	392	1			T87	1		T486	5		T828	1
values[55]	401	1			T87	1		T486	3		T828	2
values[56]	413	1			T87	1		T486	2		T828	3
values[57]	453	1			T87	1		T486	1		T828	3
values[58]	409	1			T87	1		T486	1		T828	3
values[59]	387	1			T87	1		T486	2		T828	1
values[60]	405	1			T87	2		T486	1		T828	1
values[61]	463	1			T87	1		T486	5		T828	1
values[62]	711	1			T87	1		T486	10		T828	5
values[63]	2702	1			T87	1		T486	19		T828	27
values[64]	29858	1			T87	234		T486	14		T828	80

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	546326	1			T85	32		T86	10		T87	13
values[2]	2590621	1			T85	1403		T86	954		T87	13
values[3]	1192125	1			T85	881		T86	378		T87	13
values[4]	150614	1			T85	12		T86	9		T87	14
values[5]	79258	1			T85	1		T87	13		T486	643
values[6]	51166	1			T87	13		T486	372		T828	186
values[7]	37317	1			T87	13		T486	255		T828	153
values[8]	30042	1			T87	14		T486	153		T828	135
values[9]	25634	1			T87	13		T486	97		T828	92
values[10]	22304	1			T87	13		T486	81		T828	63
values[11]	19653	1			T87	13		T486	70		T828	28
values[12]	18387	1			T87	13		T486	60		T828	13
values[13]	17478	1			T87	13		T486	48		T828	6
values[14]	16396	1			T87	13		T486	38		T828	9
values[15]	15519	1			T87	13		T486	29		T828	4
values[16]	14914	1			T87	13		T486	27		T828	7
values[17]	14134	1			T87	13		T486	28		T828	8
values[18]	13939	1			T87	13		T486	31		T828	5
values[19]	13465	1			T87	13		T486	25		T828	8
values[20]	13144	1			T87	14		T486	42		T828	6
values[21]	12619	1			T87	13		T486	29		T828	4
values[22]	11510	1			T87	13		T486	34		T828	4
values[23]	11220	1			T87	13		T486	25		T828	4
values[24]	10633	1			T87	13		T486	23		T828	11
values[25]	9936	1			T87	13		T486	24		T828	13
values[26]	9571	1			T87	14		T486	23		T828	4
values[27]	9173	1			T87	13		T486	16		T828	9
values[28]	8938	1			T87	13		T486	10		T828	8
values[29]	8523	1			T87	13		T486	21		T828	10
values[30]	8113	1			T87	14		T486	15		T828	5
values[31]	7205	1			T87	13		T486	12		T828	5
values[32]	6493	1			T87	13		T486	12		T828	5
values[33]	6172	1			T87	13		T486	28		T828	8
values[34]	5823	1			T87	13		T486	35		T828	5
values[35]	5431	1			T87	13		T486	27		T828	5
values[36]	5204	1			T87	13		T486	38		T828	13
values[37]	4956	1			T87	13		T486	14		T828	10
values[38]	4680	1			T87	13		T486	11		T828	12
values[39]	4459	1			T87	13		T486	18		T828	6
values[40]	4266	1			T87	13		T486	14		T828	6
values[41]	4227	1			T87	13		T486	12		T828	9
values[42]	4024	1			T87	13		T486	14		T828	9
values[43]	3973	1			T87	13		T486	11		T828	7
values[44]	3904	1			T87	13		T486	15		T828	7
values[45]	3973	1			T87	13		T486	15		T828	10
values[46]	3752	1			T87	13		T486	16		T828	7
values[47]	3707	1			T87	13		T486	15		T828	3
values[48]	3713	1			T87	14		T486	14		T828	8
values[49]	3664	1			T87	13		T486	21		T828	4
values[50]	3599	1			T87	13		T486	9		T828	6
values[51]	3387	1			T87	13		T486	21		T828	8
values[52]	3347	1			T87	13		T486	29		T828	11
values[53]	3281	1			T87	13		T486	19		T828	9
values[54]	3277	1			T87	13		T486	15		T828	10
values[55]	3096	1			T87	13		T486	19		T828	14
values[56]	3068	1			T87	14		T486	15		T828	8
values[57]	3099	1			T87	14		T486	15		T828	6
values[58]	2971	1			T87	14		T486	23		T828	7
values[59]	2985	1			T87	13		T486	11		T828	4
values[60]	2830	1			T87	13		T486	12		T828	11
values[61]	3026	1			T87	13		T486	24		T828	10
values[62]	4085	1			T87	14		T486	33		T828	13
values[63]	10329	1			T87	21		T486	81		T828	66
values[64]	239635	1			T87	2369		T486	215		T828	189