Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2024119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38398215

1

T4

6869

T5

3594

T6

86510

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28438603	1			T4	1451		T5	870		T6	74426
values[0x0]	10510262	1			T4	5418		T5	2724		T6	12084
values[0x1]	1473469	1			T4	107		T5	95		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	634422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39787912

1

T4

6976

T5

3689

T6

86517

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19102934	1			T4	3488		T5	1845		T6	43259
valid_sources[0x01]	19102832	1			T4	3488		T5	1844		T6	43258
valid_sources[0x02]	35211	1			T552	19		T553	14		T555	26
valid_sources[0x03]	35430	1			T79	3		T552	50		T553	18
valid_sources[0x04]	35438	1			T64	3		T199	3		T552	44
valid_sources[0x05]	35491	1			T64	4		T79	3		T199	1
valid_sources[0x06]	35527	1			T199	1		T552	53		T553	18
valid_sources[0x07]	35491	1			T552	16		T553	13		T555	15
valid_sources[0x08]	36670	1			T65	1		T199	1		T472	762
valid_sources[0x09]	35218	1			T552	23		T553	17		T555	25
valid_sources[0x0a]	35912	1			T199	1		T552	20		T553	13
valid_sources[0x0b]	35339	1			T88	1		T199	1		T552	18
valid_sources[0x0c]	35222	1			T88	1		T552	26		T553	15
valid_sources[0x0d]	35428	1			T79	1		T88	1		T552	18
valid_sources[0x0e]	35415	1			T552	35		T553	17		T555	19
valid_sources[0x0f]	35899	1			T88	1		T552	50		T553	15
valid_sources[0x10]	35708	1			T64	1		T552	34		T553	13
valid_sources[0x11]	35486	1			T79	2		T65	15		T552	24
valid_sources[0x12]	35431	1			T79	4		T199	1		T552	31
valid_sources[0x13]	35649	1			T79	1		T88	1		T199	1
valid_sources[0x14]	35033	1			T88	2		T199	1		T552	21
valid_sources[0x15]	35478	1			T552	26		T553	15		T555	20
valid_sources[0x16]	35821	1			T64	8		T88	1		T199	1
valid_sources[0x17]	36178	1			T552	46		T553	13		T555	34
valid_sources[0x18]	36408	1			T552	43		T553	16		T555	22
valid_sources[0x19]	38116	1			T552	17		T553	19		T555	23
valid_sources[0x1a]	36373	1			T79	3		T88	1		T552	49
valid_sources[0x1b]	35645	1			T64	2		T79	1		T88	1
valid_sources[0x1c]	36530	1			T79	1		T88	1		T199	2
valid_sources[0x1d]	36081	1			T64	6		T552	18		T553	19
valid_sources[0x1e]	35642	1			T65	5		T199	1		T552	17
valid_sources[0x1f]	35947	1			T88	1		T199	1		T552	23
valid_sources[0x20]	35969	1			T65	7		T199	1		T552	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27715751

1

T4

1451

T5

870

T6

74426

values[0x0]

all_enables

biggest_size

10469444

1

T4

5418

T5

2724

T6

12084

values[0x1]

all_enables

biggest_size

213020

1

T64

24

T79

16

T88

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2758183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

434736

1

T85

13

T86

181

T87

408

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1082929	1			T85	61		T86	462		T87	1073
values[0x0]	1027002	1			T85	8		T86	452		T87	1043
values[0x1]	1082988	1			T85	56		T86	416		T87	1062

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2136066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1056853

1

T85

49

T86

417

T87

1015

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50011	1			T85	5		T86	12		T87	44
valid_sources[0x01]	49836	1			T85	1		T86	10		T87	48
valid_sources[0x02]	50260	1			T85	1		T86	19		T87	52
valid_sources[0x03]	49913	1			T85	3		T86	27		T87	46
valid_sources[0x04]	50681	1			T85	3		T86	18		T87	43
valid_sources[0x05]	50335	1			T85	2		T86	13		T87	46
valid_sources[0x06]	48914	1			T85	4		T86	22		T87	51
valid_sources[0x07]	50061	1			T85	1		T86	12		T87	53
valid_sources[0x08]	49529	1			T85	1		T86	30		T87	42
valid_sources[0x09]	49641	1			T86	15		T87	49		T89	2
valid_sources[0x0a]	48947	1			T85	4		T86	30		T87	54
valid_sources[0x0b]	50050	1			T85	3		T86	42		T87	42
valid_sources[0x0c]	50260	1			T86	39		T87	48		T122	7
valid_sources[0x0d]	50193	1			T85	1		T86	33		T87	57
valid_sources[0x0e]	50658	1			T85	1		T86	15		T87	47
valid_sources[0x0f]	49767	1			T86	24		T87	55		T123	101
valid_sources[0x10]	49392	1			T85	1		T86	38		T87	49
valid_sources[0x11]	49653	1			T85	3		T86	12		T87	44
valid_sources[0x12]	50533	1			T85	3		T86	37		T87	55
valid_sources[0x13]	51715	1			T85	2		T86	15		T87	43
valid_sources[0x14]	50132	1			T85	4		T86	36		T87	50
valid_sources[0x15]	49281	1			T86	19		T87	47		T89	17
valid_sources[0x16]	50281	1			T85	3		T86	6		T87	47
valid_sources[0x17]	50794	1			T86	28		T87	56		T89	6
valid_sources[0x18]	50500	1			T85	1		T86	11		T87	62
valid_sources[0x19]	48935	1			T85	3		T86	22		T87	61
valid_sources[0x1a]	49528	1			T85	2		T86	13		T87	49
valid_sources[0x1b]	49858	1			T85	1		T86	17		T87	47
valid_sources[0x1c]	49788	1			T85	3		T86	41		T87	41
valid_sources[0x1d]	49212	1			T85	1		T86	24		T87	51
valid_sources[0x1e]	48925	1			T85	5		T86	22		T87	45
valid_sources[0x1f]	49743	1			T85	2		T86	26		T87	56
valid_sources[0x20]	49199	1			T85	1		T86	17		T87	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45897

1

T85

4

T86

18

T87

46

values[0x0]

all_enables

biggest_size

342955

1

T85

3

T86

147

T87

313

values[0x1]

all_enables

biggest_size

45884

1

T85

6

T86

16

T87

49

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2936295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477328

1

T85

20

T86

155

T87

411

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1169470	1			T85	64		T86	422		T87	1115
values[0x0]	1073846	1			T85	6		T86	361		T87	976
values[0x1]	1170307	1			T85	72		T86	407		T87	1032

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2252661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1160962

1

T85

58

T86

397

T87

1111

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53255	1			T85	1		T86	16		T87	44
valid_sources[0x01]	53273	1			T85	3		T86	25		T87	55
valid_sources[0x02]	53771	1			T85	1		T86	10		T87	30
valid_sources[0x03]	54143	1			T85	4		T86	17		T87	13
valid_sources[0x04]	53893	1			T85	2		T86	21		T87	33
valid_sources[0x05]	54478	1			T85	2		T86	19		T87	100
valid_sources[0x06]	53104	1			T86	30		T87	40		T89	5
valid_sources[0x07]	54178	1			T85	4		T86	12		T87	76
valid_sources[0x08]	54035	1			T85	1		T86	17		T87	33
valid_sources[0x09]	52655	1			T85	4		T86	18		T87	54
valid_sources[0x0a]	52936	1			T85	1		T86	25		T87	55
valid_sources[0x0b]	52872	1			T85	5		T86	8		T87	40
valid_sources[0x0c]	54076	1			T85	1		T86	10		T87	25
valid_sources[0x0d]	54463	1			T85	2		T86	15		T87	51
valid_sources[0x0e]	52840	1			T85	5		T86	16		T87	63
valid_sources[0x0f]	53708	1			T85	1		T86	26		T87	53
valid_sources[0x10]	53187	1			T85	1		T86	24		T87	51
valid_sources[0x11]	53398	1			T85	3		T86	28		T87	47
valid_sources[0x12]	52744	1			T85	1		T86	8		T87	29
valid_sources[0x13]	53019	1			T85	1		T86	31		T87	38
valid_sources[0x14]	53226	1			T85	2		T86	22		T87	38
valid_sources[0x15]	53315	1			T86	28		T87	39		T89	2
valid_sources[0x16]	54187	1			T85	7		T86	20		T87	25
valid_sources[0x17]	54307	1			T85	3		T86	23		T87	45
valid_sources[0x18]	53133	1			T86	22		T87	38		T124	5
valid_sources[0x19]	52834	1			T85	1		T86	22		T87	63
valid_sources[0x1a]	53326	1			T85	6		T86	13		T87	74
valid_sources[0x1b]	52248	1			T86	14		T87	72		T89	2
valid_sources[0x1c]	53667	1			T85	2		T86	8		T87	82
valid_sources[0x1d]	53488	1			T85	2		T86	14		T87	45
valid_sources[0x1e]	53774	1			T85	6		T86	11		T87	29
valid_sources[0x1f]	52878	1			T85	1		T86	13		T87	71
valid_sources[0x20]	53101	1			T85	3		T86	23		T87	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50523

1

T85

7

T86

12

T87

41

values[0x0]

all_enables

biggest_size

376751

1

T85

2

T86

126

T87

328

values[0x1]

all_enables

biggest_size

50054

1

T85

11

T86

17

T87

42

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2782210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

440204

1

T85

6

T86

178

T87

438

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1092820	1			T85	43		T86	443		T87	1087
values[0x0]	1037352	1			T85	8		T86	457		T87	1044
values[0x1]	1092242	1			T85	52		T86	451		T87	1075

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2153385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1069029

1

T85

44

T86

440

T87

1055

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50573	1			T85	3		T86	5		T87	61
valid_sources[0x01]	50273	1			T85	1		T86	17		T87	51
valid_sources[0x02]	50779	1			T85	1		T86	37		T87	48
valid_sources[0x03]	50121	1			T85	2		T86	25		T87	57
valid_sources[0x04]	50572	1			T86	17		T87	46		T89	5
valid_sources[0x05]	50598	1			T86	18		T87	48		T89	6
valid_sources[0x06]	50391	1			T85	1		T86	19		T87	54
valid_sources[0x07]	50224	1			T85	4		T86	37		T87	47
valid_sources[0x08]	49896	1			T85	3		T86	33		T87	54
valid_sources[0x09]	50440	1			T85	1		T86	37		T87	54
valid_sources[0x0a]	50631	1			T85	1		T86	49		T87	52
valid_sources[0x0b]	50490	1			T85	1		T86	31		T87	50
valid_sources[0x0c]	50025	1			T85	2		T86	31		T87	53
valid_sources[0x0d]	49862	1			T86	44		T87	40		T89	5
valid_sources[0x0e]	50155	1			T85	1		T86	7		T87	49
valid_sources[0x0f]	50701	1			T85	1		T86	18		T87	60
valid_sources[0x10]	50789	1			T85	3		T86	7		T87	37
valid_sources[0x11]	50988	1			T85	3		T86	12		T87	53
valid_sources[0x12]	50503	1			T86	10		T87	55		T124	1
valid_sources[0x13]	49842	1			T85	2		T86	5		T87	60
valid_sources[0x14]	51347	1			T86	2		T87	56		T89	2
valid_sources[0x15]	50475	1			T85	2		T86	8		T87	45
valid_sources[0x16]	50374	1			T86	17		T87	56		T89	2
valid_sources[0x17]	50440	1			T85	1		T86	24		T87	50
valid_sources[0x18]	51058	1			T85	2		T86	15		T87	46
valid_sources[0x19]	49679	1			T85	1		T86	45		T87	58
valid_sources[0x1a]	50120	1			T85	2		T86	38		T87	49
valid_sources[0x1b]	49252	1			T85	3		T86	22		T87	42
valid_sources[0x1c]	50337	1			T85	2		T86	16		T87	45
valid_sources[0x1d]	49666	1			T86	10		T87	40		T124	2
valid_sources[0x1e]	51259	1			T85	1		T86	44		T87	49
valid_sources[0x1f]	49745	1			T85	4		T86	8		T87	48
valid_sources[0x20]	50212	1			T86	6		T87	49		T89	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46294

1

T85

2

T86

14

T87

57

values[0x0]

all_enables

biggest_size

347169

1

T85

3

T86

143

T87

329

values[0x1]

all_enables

biggest_size

46741

1

T85

1

T86

21

T87

52