Unified Coverage Report :: Module :: adc_ctrl

Module : adc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : adc_ctrl

	Total	Covered	Percent
Totals	37	37	100.00
Total Bits	324	324	100.00
Total Bits 0->1	162	162	100.00
Total Bits 1->0	162	162	100.00

Ports	37	37	100.00
Port Bits	324	324	100.00
Port Bits 0->1	162	162	100.00
Port Bits 1->0	162	162	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T42,T18	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T4,T42,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[17:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_i.a_valid	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_o.a_ready	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_o.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T71,*T1,*T2	Yes	T71,T1,T2	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T92,T93	Yes	T70,T92,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T157	Yes	T92,T93,T157	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T157	Yes	T92,T93,T157	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T92,T93	Yes	T70,T92,T93	OUTPUT
adc_o.pd	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
adc_o.channel_sel[1:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
adc_i.data_valid	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
adc_i.data[9:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
intr_match_pending_o	Yes	Yes	T71,T321,T326	Yes	T71,T321,T326	OUTPUT
wkup_req_o	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT

*Tests covering at least one bit in the range