Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T64,*T79,*T88 Yes T64,T79,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T64,T79,T88 Yes T64,T79,T88 INPUT
tl_i.a_valid Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_o.a_ready Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_error Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_sink Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_source[5:0] Yes Yes *T257,*T258,*T710 Yes T257,T258,T710 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T56,*T105 Yes T6,T56,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T70,T711,T91 Yes T70,T711,T91 INPUT
alert_rx_i[0].ping_n Yes Yes T70,T91,T102 Yes T91,T102,T92 INPUT
alert_rx_i[0].ping_p Yes Yes T91,T102,T92 Yes T70,T91,T102 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T70,T711,T91 Yes T70,T711,T91 OUTPUT
cio_rx_i Yes Yes T4,T42,T18 Yes T4,T5,T43 INPUT
cio_tx_o Yes Yes T6,T56,T57 Yes T6,T56,T57 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T105,T106,T212 Yes T105,T106,T212 OUTPUT
intr_tx_empty_o Yes Yes T106,T212,T216 Yes T106,T212,T216 OUTPUT
intr_rx_watermark_o Yes Yes T106,T212,T216 Yes T106,T212,T216 OUTPUT
intr_tx_done_o Yes Yes T106,T212,T216 Yes T106,T212,T216 OUTPUT
intr_rx_overflow_o Yes Yes T106,T212,T216 Yes T106,T212,T216 OUTPUT
intr_rx_frame_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_break_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_timeout_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_parity_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T64,*T79,*T88 Yes T64,T79,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T64,T79,T88 Yes T64,T79,T88 INPUT
tl_i.a_valid Yes Yes T6,T56,T105 Yes T6,T56,T105 INPUT
tl_o.a_ready Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_error Yes Yes T85,T86,T89 Yes T85,T86,T89 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
tl_o.d_sink Yes Yes T85,T86,T124 Yes T85,T86,T87 OUTPUT
tl_o.d_source[5:0] Yes Yes *T257,*T258,*T710 Yes T257,T258,T710 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T124 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T56,*T105 Yes T6,T56,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T56,T105 Yes T6,T56,T105 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T711,T91,T102 Yes T711,T91,T102 INPUT
alert_rx_i[0].ping_n Yes Yes T91,T102,T92 Yes T91,T102,T92 INPUT
alert_rx_i[0].ping_p Yes Yes T91,T102,T92 Yes T91,T102,T92 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T711,T91,T102 Yes T711,T91,T102 OUTPUT
cio_rx_i Yes Yes T4,T42,T18 Yes T4,T5,T43 INPUT
cio_tx_o Yes Yes T6,T56,T57 Yes T6,T56,T57 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T105,T216,T308 Yes T105,T216,T308 OUTPUT
intr_tx_empty_o Yes Yes T216,T308,T333 Yes T216,T308,T333 OUTPUT
intr_rx_watermark_o Yes Yes T216,T308,T333 Yes T216,T308,T333 OUTPUT
intr_tx_done_o Yes Yes T216,T308,T336 Yes T216,T308,T336 OUTPUT
intr_rx_overflow_o Yes Yes T216,T308,T336 Yes T216,T308,T336 OUTPUT
intr_rx_frame_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_break_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_timeout_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_parity_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T106,T212,T213 Yes T106,T212,T213 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T106,T212,T213 Yes T106,T212,T213 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T64,*T79,*T88 Yes T64,T79,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T64,T79,T88 Yes T64,T79,T88 INPUT
tl_i.a_valid Yes Yes T106,T212,T213 Yes T106,T212,T213 INPUT
tl_o.a_ready Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
tl_o.d_error Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
tl_o.d_data[31:0] Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
tl_o.d_sink Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_source[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T106,*T212,*T213 Yes T106,T212,T213 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T70,T92,T93 Yes T70,T92,T93 INPUT
alert_rx_i[0].ping_n Yes Yes T70,T92,T93 Yes T92,T93,T157 INPUT
alert_rx_i[0].ping_p Yes Yes T92,T93,T157 Yes T70,T92,T93 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T70,T92,T93 Yes T70,T92,T93 OUTPUT
cio_rx_i Yes Yes T106,T212,T213 Yes T106,T212,T213 INPUT
cio_tx_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
intr_tx_empty_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
intr_rx_watermark_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
intr_tx_done_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
intr_rx_overflow_o Yes Yes T106,T212,T213 Yes T106,T212,T213 OUTPUT
intr_rx_frame_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_break_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_timeout_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_parity_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T146,T147,T334 Yes T146,T147,T334 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T146,T147,T334 Yes T146,T147,T334 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T64,*T79,*T88 Yes T64,T79,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T64,T79,T88 Yes T64,T79,T88 INPUT
tl_i.a_valid Yes Yes T146,T147,T334 Yes T146,T147,T334 INPUT
tl_o.a_ready Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
tl_o.d_error Yes Yes T85,T86,T89 Yes T85,T86,T89 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
tl_o.d_data[31:0] Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
tl_o.d_sink Yes Yes T85,T86,T89 Yes T85,T86,T89 OUTPUT
tl_o.d_source[5:0] Yes Yes *T85,*T86,*T123 Yes T85,T86,T89 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T85,T86,T89 Yes T85,T86,T89 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T146,*T147,*T334 Yes T146,T147,T334 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T91,T102,T92 Yes T91,T102,T92 INPUT
alert_rx_i[0].ping_n Yes Yes T91,T102,T92 Yes T91,T102,T92 INPUT
alert_rx_i[0].ping_p Yes Yes T91,T102,T92 Yes T91,T102,T92 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T91,T102,T92 Yes T91,T102,T92 OUTPUT
cio_rx_i Yes Yes T146,T147,T334 Yes T146,T147,T334 INPUT
cio_tx_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
intr_tx_empty_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
intr_rx_watermark_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
intr_tx_done_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
intr_rx_overflow_o Yes Yes T146,T147,T334 Yes T146,T147,T334 OUTPUT
intr_rx_frame_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_break_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_timeout_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_parity_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T19,T27,T28 Yes T19,T27,T28 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T19,T27,T28 Yes T19,T27,T28 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T64,*T79,*T88 Yes T64,T79,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T64,T79,T88 Yes T64,T79,T88 INPUT
tl_i.a_valid Yes Yes T19,T27,T28 Yes T19,T27,T28 INPUT
tl_o.a_ready Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
tl_o.d_error Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
tl_o.d_data[31:0] Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
tl_o.d_sink Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_source[5:0] Yes Yes *T85,*T86,*T87 Yes T85,T86,T87 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T19,*T27,*T28 Yes T19,T27,T28 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T92,T93,T157 Yes T92,T93,T157 INPUT
alert_rx_i[0].ping_n Yes Yes T92,T93,T157 Yes T92,T93,T157 INPUT
alert_rx_i[0].ping_p Yes Yes T92,T93,T157 Yes T92,T93,T157 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T92,T93,T157 Yes T92,T93,T157 OUTPUT
cio_rx_i Yes Yes T19,T27,T28 Yes T19,T27,T28 INPUT
cio_tx_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
intr_tx_empty_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
intr_rx_watermark_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
intr_tx_done_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
intr_rx_overflow_o Yes Yes T19,T27,T28 Yes T19,T27,T28 OUTPUT
intr_rx_frame_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_break_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_timeout_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT
intr_rx_parity_err_o Yes Yes T322,T324,T325 Yes T322,T324,T325 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%