Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T85,T248,T249	Yes	T85,T248,T249	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T4,T18,T100	Yes	T4,T18,T100	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T100	Yes	T4,T18,T100	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T79,T208,T65	Yes	T79,T208,T65	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T79,T208,T65	Yes	T79,T208,T65	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T42,T18	Yes	T4,T42,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T87	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T85,T86,*T87	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T89	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T256,*T257,*T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T256,*T257,*T258	Yes	T256,T257,T258	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T42,T71	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T256,T257,T258	Yes	T256,T257,T258	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T6,T96,T56	Yes	T6,T96,T56	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T86,T89	Yes	T66,T67,T68	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T274,*T410,*T411	Yes	T274,T409,T410	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T274,T409,T410	Yes	T274,T409,T410	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T74,T356,T335	Yes	T74,T356,T335	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T209,T24,T385	Yes	T209,T24,T385	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T209,T24,T385	Yes	T209,T24,T385	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T25,T197,T198	Yes	T25,T197,T198	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T209,T24,T385	Yes	T209,T24,T385	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T209,T24,T385	Yes	T209,T24,T385	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T123	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T89	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T85,T86,T122	Yes	T85,T86,T124	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T105,*T209,*T24	Yes	T105,T209,T24	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T105,T209,T24	Yes	T105,T209,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T209,T385,T154	Yes	T209,T385,T154	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T209,T385,T154	Yes	T209,T385,T154	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T209,T385,T154	Yes	T209,T385,T154	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T209,T385,T154	Yes	T209,T385,T154	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T105,*T209,*T385	Yes	T105,T209,T385	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T105,T209,T385	Yes	T105,T209,T385	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T2,T29	Yes	T1,T2,T29	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_usbdev_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T105,T29,T30	Yes	T105,T29,T30	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T105,T29,T30	Yes	T105,T29,T30	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T105,T2	Yes	T105,T2,T29	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T105,*T2	Yes	T105,T2,T29	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T105,T2	Yes	T1,T105,T2	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T124	Yes	T85,T86,T124	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T6,T42	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T124	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T85,T86,T122	Yes	T85,T86,T89	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T85,*T472,*T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T85,T472,T86	Yes	T85,T472,T86	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T97,T297,T704	Yes	T97,T297,T704	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	INPUT
tl_hmac_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_hmac_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T89	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T6,*T56,*T57	Yes	T6,T56,T57	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T6,T193,T56	Yes	T6,T193,T56	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T98,T152,T153	Yes	T98,T152,T153	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T98,T152,T153	Yes	T98,T152,T153	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T85	Yes	T64,T65,T85	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T98,T152,T480	Yes	T98,T152,T480	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	INPUT
tl_kmac_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T98,T152,T153	Yes	T98,T152,T64	INPUT
tl_kmac_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T89	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T85	Yes	T64,T65,T85	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T98,*T152,*T153	Yes	T98,T152,T64	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T193,T98,T152	Yes	T193,T98,T152	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T701,T296,T116	Yes	T701,T296,T116	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T701,T296,T116	Yes	T701,T296,T116	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T701,T296,T116	Yes	T701,T296,T116	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	INPUT
tl_aes_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T89	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T701,T259,T296	Yes	T701,T259,T296	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	INPUT
tl_aes_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T87	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T193,*T701,*T259	Yes	T193,T701,T259	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T193,T701,T259	Yes	T193,T701,T259	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T71,*T121,*T101	Yes	T6,T71,T56	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T71,*T121,*T101	Yes	T71,T121,T101	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T89	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T71,*T121,*T101	Yes	T71,T121,T101	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_edn1_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T87	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_edn1_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T87	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T87	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T71,*T121,*T101	Yes	T71,T121,T101	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T71,T121,T101	Yes	T71,T121,T101	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T89	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T6,T43	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T43,T193	Yes	T6,T43,T193	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T6,T43,T193	Yes	T6,T43,T193	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T6,T43,T193	Yes	T6,T43,T193	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T208	Yes	T64,T79,T208	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T6,T43,T193	Yes	T6,T43,T193	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T6,T43,T193	Yes	T6,T43,T193	INPUT
tl_otbn_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T122	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	INPUT
tl_otbn_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T89	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T208	Yes	T64,T79,T208	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T6,*T43,*T56	Yes	T6,T43,T56	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T6,T43,T56	Yes	T6,T43,T56	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T57,T108,T59	Yes	T57,T108,T59	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_keymgr_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T59,T152,T153	Yes	T59,T152,T153	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T6,*T56,*T57	Yes	T6,T56,T57	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T258,*T85,*T86	Yes	T258,T85,T86	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T258,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T471,*T85,*T86	Yes	T471,T85,T86	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T18,T181,T305	Yes	T18,T181,T305	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T53,T54	Yes	T6,T18,T56	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T18,T53,T54	Yes	T6,T18,T56	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T124	Yes	T471,T85,T86	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T124	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T18,*T115,*T178	Yes	T18,T115,T178	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T6,T18,T56	Yes	T6,T18,T56	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range