dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[21].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[22].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[23].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[24].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[25].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[26].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[27].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[28].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[29].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[30].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[31].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[32].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[33].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[34].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[35].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[36].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[37].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[38].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[39].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[40].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[41].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[42].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT5,T215,T109
01CoveredT215,T109,T103
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT109,T214,T35
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT5,T215,T109

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT5,T215,T109
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T215,T109

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT5,T215,T109

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T5,T215,T109
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT6,T19,T56
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T39,T40
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T39,T40

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T56,T57

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T39,T40
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T6,T56,T57
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT19,T21,T142
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T23,T39
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T187
11CoveredT21,T23,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T23,T39
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T23,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T23,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T56,T57

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T23,T39
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T6,T56,T57
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT19,T21,T142
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T39,T40
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T39,T40
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T39,T40

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T56,T57

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T39,T40
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T6,T56,T57
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT216,T64,T79
01CoveredT4,T5,T43
10CoveredT39,T40,T41
11CoveredT39,T41,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT23,T39,T40
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT23,T39,T40

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT23,T39,T40
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT23,T39,T40

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT23,T39,T40

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T43

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T23,T39,T40
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T43
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T56,T57
01CoveredT4,T5,T6
10CoveredT40,T41,T187
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT4,T5,T6
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT4,T5,T6
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT59,T64,T79
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT22,T39,T40
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT22,T23,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT22,T23,T39
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT22,T23,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT22,T23,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T23,T39
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT61,T63,T117
01CoveredT61,T63,T117
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T22,T23
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT40,T41,T187
11CoveredT21,T22,T23

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T187

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T22,T23
11CoveredT39,T40,T187

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T22,T23

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T187
11CoveredT21,T22,T23

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T187
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T22,T23
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT177,T29,T64
01CoveredT177,T29,T202
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T31,T22
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T31,T22

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T31,T22
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T31,T22

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T31,T22

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T31,T22
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT61,T62,T63
10CoveredT39,T40,T41
11CoveredT39,T41,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT23,T39,T40
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T23,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T23,T39
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T23,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T23,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T23,T39
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT177,T64,T79
01CoveredT177,T202,T21
10CoveredT40,T41,T187
11CoveredT40,T187,T188

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT35,T31,T36
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T187
11CoveredT35,T31,T36

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT35,T31,T36
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT35,T31,T36

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T31,T36

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T35,T31,T36
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT109,T64,T79
01CoveredT109,T35,T148
10CoveredT39,T40,T187
11CoveredT39,T40,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT109,T35,T148
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT109,T21,T35

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT109,T21,T35
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT109,T21,T35

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT109,T21,T35

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T109,T21,T35
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT109,T64,T79
01CoveredT109,T21,T35
10CoveredT39,T41,T187
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT109,T21,T35
11CoveredT39,T41,T187

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T187
11CoveredT109,T21,T35

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT109,T21,T35
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT109,T21,T35

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT109,T21,T35

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T109,T21,T35
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT109,T64,T79
01CoveredT109,T21,T35
10CoveredT39,T41,T187
11CoveredT39,T41,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT109,T21,T35
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T187
11CoveredT109,T21,T35

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT109,T21,T35
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT109,T21,T35

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT109,T21,T35

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T109,T21,T35
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT61,T62,T63
01CoveredT62,T63,T58
10CoveredT39,T40,T187
11CoveredT39,T40,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T35,T36
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T36

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T35,T36
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T35,T36

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T36

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T35,T36
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT62,T63,T58
01CoveredT62,T63,T58
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT62,T63,T58
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT62,T63,T58

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT62,T63,T58
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT62,T63,T58

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT62,T63,T58

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T62,T63,T58
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT61,T62,T63
01CoveredT62,T63,T58
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT35,T36,T94
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T36,T94

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT35,T36,T94
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT35,T36,T94

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T36,T94

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T35,T36,T94
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT62,T63,T58
01CoveredT61,T62,T63
10CoveredT39,T40,T41
11CoveredT40,T41,T187

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT35,T36,T94
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T36,T94

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT35,T36,T94
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT35,T36,T94

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T36,T94

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T35,T36,T94
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT61,T62,T63
01CoveredT61,T62,T63
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT35,T36,T94
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T36

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T35,T36
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T35,T36

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T36

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T35,T36
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT21,T81,T35
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T35,T31
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T35,T31
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T35,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T35,T31
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT64,T79,T88
01CoveredT21,T35,T31
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT21,T35,T31
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T187
11CoveredT21,T35,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T35,T31
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T35,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T35,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T35,T31
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT21,T217,T35
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT35,T36,T22
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T187
11CoveredT35,T36,T22

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT35,T36,T22
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT35,T36,T22

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT35,T36,T22

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T35,T36,T22
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1017 1017 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T42 1 1 0 0
T43 1 1 0 0
T70 1 1 0 0
T71 1 1 0 0
T95 1 1 0 0
T96 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%