Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T74,T356,T335	Yes	T74,T356,T335	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	INPUT
tl_uart0_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	INPUT
tl_uart0_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T87	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T257,*T258,*T710	Yes	T257,T258,T710	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T124	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T6,*T56,*T105	Yes	T6,T56,T105	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T6,T56,T105	Yes	T6,T56,T105	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	INPUT
tl_uart1_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	INPUT
tl_uart1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T106,*T212,*T213	Yes	T106,T212,T213	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T106,T212,T213	Yes	T106,T212,T213	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	INPUT
tl_uart2_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	INPUT
tl_uart2_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T123	Yes	T85,T86,T89	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T146,*T147,*T334	Yes	T146,T147,T334	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T146,T147,T334	Yes	T146,T147,T334	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	INPUT
tl_uart3_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	INPUT
tl_uart3_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T19,*T27,*T28	Yes	T19,T27,T28	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T19,T27,T28	Yes	T19,T27,T28	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	INPUT
tl_i2c0_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T89	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T211,T321,T328	Yes	T211,T321,T328	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T211,*T209,*T385	Yes	T211,T209,T385	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T211,T209,T385	Yes	T211,T209,T385	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	INPUT
tl_i2c1_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T321,T327,T326	Yes	T321,T327,T326	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T209,*T385,*T321	Yes	T209,T385,T321	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T209,T385,T321	Yes	T209,T385,T321	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	INPUT
tl_i2c2_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T215,T103,T321	Yes	T215,T103,T321	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T87	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T215,*T103,*T209	Yes	T215,T103,T209	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T215,T103,T209	Yes	T215,T103,T209	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	INPUT
tl_pattgen_i.d_error	Yes	Yes	T85,T124,T122	Yes	T85,T124,T122	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T64,*T65,T85	Yes	T64,T65,T85	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T85,T86,T122	Yes	T85,T86,T124	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T5,*T64,*T214	Yes	T5,T64,T214	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T5,T64,T214	Yes	T5,T64,T214	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T85,*T86,*T122	Yes	T85,T86,T89	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T109,*T148,*T702	Yes	T109,T148,T702	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T109,T148,T702	Yes	T109,T148,T702	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T35,T321,T36	Yes	T35,T321,T36	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T148,T321	Yes	T35,T3,T148	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T35,T148,T321	Yes	T35,T3,T148	INPUT
tl_gpio_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T42,*T71	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	INPUT
tl_spi_device_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T123	Yes	T85,T86,T89	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T19,*T209,*T24	Yes	T19,T209,T24	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T19,T209,T24	Yes	T19,T209,T24	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T122	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T253,T315,T154	Yes	T253,T315,T154	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T85,T86,T124	Yes	T85,T86,T122	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T124	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T85,T86,T122	Yes	T85,T86,T124	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T344,*T253,*T148	Yes	T344,T253,T148	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T344,T253,T148	Yes	T344,T253,T148	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T95	Yes	T6,T17,T95	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T17,T95	Yes	T6,T17,T95	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T95	Yes	T6,T17,T95	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T95	Yes	T4,T6,T17	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T95	Yes	T4,T6,T17	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T95	Yes	T6,T17,T95	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T42	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T61,T19,T193	Yes	T61,T19,T193	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T71,T61,T19	Yes	T71,T61,T19	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T61,T19,T106	Yes	T61,T19,T106	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T42,T18	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T42,T18	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T170,T708	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T61,*T19,*T193	Yes	T61,T19,T193	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T85	Yes	T64,T65,T85	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T43	Yes	T4,T5,T43	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T85,T86,T124	Yes	T85,T86,T122	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T124	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T142	Yes	T64,T65,T142	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T85,T86,T122	Yes	T85,T86,T124	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T18,*T152,*T153	Yes	T18,T152,T153	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T42,T71	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T64,*T65,T85	Yes	T64,T65,T85	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T42,T71	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T64,T65,T85	Yes	T64,T65,T85	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T56	Yes	T6,T19,T56	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T58,T73	Yes	T72,T58,T73	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T124	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T373	Yes	T64,T65,T373	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T72	Yes	T6,T18,T19	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T71,T1,T54	Yes	T71,T1,T54	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T1,T54	Yes	T71,T1,T54	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T43	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T42,*T71	Yes	T4,T5,T43	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T17,T42	Yes	T4,T17,T42	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T17,*T42	Yes	T4,T6,T17	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T115,T178,T179	Yes	T115,T178,T179	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T54,T115	Yes	T6,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T53,T54,T115	Yes	T6,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T115,*T178,*T179	Yes	T115,T178,T179	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T6,T56,T57	Yes	T6,T56,T57	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T42,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T79,*T208,*T257	Yes	T79,T208,T257	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T85,T86,T123	Yes	T85,T86,T89	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T95	Yes	T4,T17,T95	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T124	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T257,T471	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T89	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T17	Yes	T4,T6,T17	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T20,T2	Yes	T1,T20,T2	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T177,T20,T487	Yes	T177,T1,T20	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T89	Yes	T85,T86,T89	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T20,*T2	Yes	T177,T1,T20	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T177,T1,T20	Yes	T177,T1,T20	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T88,*T85,*T86	Yes	T88,T85,T86	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T124	Yes	T85,T86,T124	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T71,*T1,*T2	Yes	T71,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T71,T1,T2	Yes	T71,T1,T2	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T64,*T79,*T88	Yes	T64,T79,T88	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T64,T79,T88	Yes	T64,T79,T88	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T89	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T42,T71	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T85,T86,T122	Yes	T85,T86,T89	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T122	Yes	T85,T86,T122	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T85,T86,T123	Yes	T85,T86,T89	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T124	Yes	T85,T86,T89	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range