Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1017	1017	0	0
OutputsKnown_A	135274924	134600527	0	0
gen_no_flops.OutputDelay_A	135274924	134600527	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135274924	134600527	0	0
T4	52093	51567	0	0
T5	17769	17119	0	0
T6	227469	226864	0	0
T17	42484	41874	0	0
T42	59184	58827	0	0
T43	35866	35260	0	0
T70	41154	40706	0	0
T71	329289	328537	0	0
T95	31036	30325	0	0
T96	11050	10502	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135274924	134600527	0	0
T4	52093	51567	0	0
T5	17769	17119	0	0
T6	227469	226864	0	0
T17	42484	41874	0	0
T42	59184	58827	0	0
T43	35866	35260	0	0
T70	41154	40706	0	0
T71	329289	328537	0	0
T95	31036	30325	0	0
T96	11050	10502	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1017	1017	0	0
OutputsKnown_A	135274924	134600527	0	0
gen_no_flops.OutputDelay_A	135274924	134600527	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135274924	134600527	0	0
T4	52093	51567	0	0
T5	17769	17119	0	0
T6	227469	226864	0	0
T17	42484	41874	0	0
T42	59184	58827	0	0
T43	35866	35260	0	0
T70	41154	40706	0	0
T71	329289	328537	0	0
T95	31036	30325	0	0
T96	11050	10502	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135274924	134600527	0	0
T4	52093	51567	0	0
T5	17769	17119	0	0
T6	227469	226864	0	0
T17	42484	41874	0	0
T42	59184	58827	0	0
T43	35866	35260	0	0
T70	41154	40706	0	0
T71	329289	328537	0	0
T95	31036	30325	0	0
T96	11050	10502	0	0