Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143547	1			T75	8		T76	62		T77	5
values[2]	10667	1			T76	1		T78	1		T543	2
values[3]	3889	1			T457	16		T540	19		T699	73
values[4]	2220	1			T457	8		T540	1		T699	37
values[5]	1375	1			T457	18		T699	21		T578	8
values[6]	956	1			T457	14		T699	11		T578	9
values[7]	749	1			T457	12		T699	3		T578	3
values[8]	569	1			T457	7		T578	5		T700	4
values[9]	400	1			T457	8		T578	4		T700	6
values[10]	454	1			T457	11		T578	7		T700	1
values[11]	417	1			T457	8		T578	27		T700	1
values[12]	339	1			T457	6		T578	8		T700	4
values[13]	317	1			T457	8		T578	6		T700	13
values[14]	335	1			T457	10		T578	5		T700	9
values[15]	312	1			T457	5		T578	5		T700	5
values[16]	338	1			T457	9		T578	10		T700	7
values[17]	318	1			T457	8		T578	8		T700	2
values[18]	326	1			T457	4		T578	10		T700	2
values[19]	301	1			T457	10		T578	8		T700	1
values[20]	299	1			T457	6		T578	10		T700	2
values[21]	328	1			T457	11		T578	12		T700	2
values[22]	288	1			T457	3		T578	7		T700	2
values[23]	284	1			T457	6		T578	9		T700	1
values[24]	275	1			T457	11		T578	3		T700	6
values[25]	285	1			T457	8		T578	6		T700	7
values[26]	321	1			T457	6		T578	5		T700	11
values[27]	295	1			T457	5		T578	6		T700	7
values[28]	259	1			T457	6		T578	6		T700	5
values[29]	231	1			T457	5		T578	7		T700	2
values[30]	278	1			T457	3		T578	6		T700	6
values[31]	273	1			T457	11		T578	8		T700	2
values[32]	280	1			T457	14		T578	12		T700	3
values[33]	314	1			T457	10		T578	27		T700	5
values[34]	302	1			T457	6		T578	4		T700	12
values[35]	300	1			T457	3		T578	3		T700	15
values[36]	322	1			T457	3		T578	5		T700	9
values[37]	286	1			T457	6		T578	9		T700	5
values[38]	261	1			T457	6		T578	6		T700	4
values[39]	287	1			T457	3		T578	5		T700	6
values[40]	294	1			T457	5		T578	3		T700	3
values[41]	277	1			T457	6		T578	6		T700	6
values[42]	287	1			T457	3		T578	18		T700	3
values[43]	357	1			T457	17		T578	6		T700	1
values[44]	247	1			T457	12		T578	8		T700	3
values[45]	261	1			T457	12		T578	8		T700	2
values[46]	301	1			T457	2		T578	6		T700	4
values[47]	274	1			T457	10		T578	6		T700	5
values[48]	260	1			T457	6		T578	6		T700	5
values[49]	257	1			T457	6		T578	4		T700	1
values[50]	205	1			T457	4		T578	3		T700	2
values[51]	235	1			T457	5		T578	5		T700	4
values[52]	220	1			T457	8		T578	15		T700	4
values[53]	170	1			T457	3		T578	10		T700	7
values[54]	257	1			T457	3		T578	17		T700	3
values[55]	237	1			T457	10		T578	10		T700	1
values[56]	179	1			T457	12		T578	7		T700	3
values[57]	227	1			T457	14		T578	4		T700	4
values[58]	191	1			T457	12		T700	3		T466	7
values[59]	191	1			T457	4		T700	1		T466	9
values[60]	206	1			T457	8		T700	1		T466	9
values[61]	192	1			T457	10		T700	6		T466	6
values[62]	172	1			T457	2		T700	5		T466	5
values[63]	191	1			T700	1		T466	5		T483	1
values[64]	161	1			T700	4		T466	1		T483	1
values[65]	139	1			T700	13		T483	1		T459	12
values[66]	148	1			T700	7		T483	1		T459	21
values[67]	128	1			T700	1		T483	1		T459	13
values[68]	99	1			T700	2		T483	1		T459	7
values[69]	98	1			T700	1		T483	1		T509	6
values[70]	113	1			T700	3		T483	1		T509	2
values[71]	90	1			T700	2		T483	1		T509	9
values[72]	72	1			T700	3		T483	1		T509	10
values[73]	76	1			T700	7		T483	1		T509	14
values[74]	73	1			T700	3		T483	1		T509	9
values[75]	76	1			T700	7		T483	1		T509	9
values[76]	61	1			T700	3		T483	1		T509	6
values[77]	75	1			T700	3		T483	1		T509	7
values[78]	70	1			T700	1		T483	1		T509	4
values[79]	52	1			T700	2		T483	1		T509	6
values[80]	59	1			T700	2		T483	1		T509	4
values[81]	78	1			T700	3		T483	2		T509	10
values[82]	76	1			T700	4		T483	1		T509	4
values[83]	79	1			T700	3		T483	1		T509	2
values[84]	72	1			T700	3		T483	1		T509	6
values[85]	70	1			T700	3		T483	1		T509	7
values[86]	84	1			T700	1		T483	1		T509	10
values[87]	86	1			T483	1		T509	1		T477	6
values[88]	66	1			T483	1		T477	4		T571	1
values[89]	69	1			T483	1		T477	3		T571	1
values[90]	75	1			T483	1		T477	2		T571	1
values[91]	60	1			T483	1		T477	1		T571	1
values[92]	92	1			T483	1		T477	2		T571	1
values[93]	68	1			T483	1		T477	3		T571	1
values[94]	62	1			T483	1		T477	6		T571	1
values[95]	68	1			T483	1		T477	6		T571	1
values[96]	67	1			T483	1		T477	7		T571	1
values[97]	58	1			T483	1		T477	3		T571	1
values[98]	73	1			T483	1		T477	6		T571	1
values[99]	77	1			T483	1		T477	4		T571	2
values[100]	58	1			T483	2		T477	9		T571	3
values[101]	63	1			T483	3		T477	7		T571	1
values[102]	63	1			T483	3		T477	6		T571	1
values[103]	71	1			T483	1		T477	2		T571	1
values[104]	78	1			T483	5		T477	11		T571	1
values[105]	73	1			T483	4		T477	4		T571	1
values[106]	59	1			T483	1		T477	1		T571	1
values[107]	51	1			T483	2		T477	1		T571	3
values[108]	67	1			T483	1		T477	5		T571	5
values[109]	67	1			T483	2		T477	7		T571	2
values[110]	63	1			T483	1		T477	4		T571	8
values[111]	67	1			T483	7		T477	4		T571	3
values[112]	67	1			T483	5		T477	3		T571	3
values[113]	53	1			T483	2		T477	2		T571	2
values[114]	60	1			T483	1		T477	1		T571	1
values[115]	55	1			T483	4		T477	2		T571	2
values[116]	58	1			T483	1		T477	1		T571	1
values[117]	55	1			T483	3		T477	1		T571	1
values[118]	67	1			T483	2		T477	1		T571	5
values[119]	49	1			T483	1		T477	3		T571	1
values[120]	51	1			T483	1		T477	6		T571	5
values[121]	64	1			T483	2		T477	2		T571	3
values[122]	65	1			T483	8		T477	4		T571	1
values[123]	59	1			T483	4		T477	2		T571	2
values[124]	55	1			T483	1		T477	5		T571	3
values[125]	74	1			T483	1		T477	12		T571	1
values[126]	103	1			T483	9		T477	24		T571	3
values[127]	889	1			T483	26		T477	37		T571	41
values[128]	7886	1			T483	319		T477	21		T571	312