Name |
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.69730326 |
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.147587299 |
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2763880257 |
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.641724354 |
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2732871711 |
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2648043858 |
/workspace/coverage/cover_reg_top/0.chip_tl_errors.866046759 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2919396660 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3724337565 |
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2355985918 |
/workspace/coverage/cover_reg_top/0.xbar_error_random.3517702082 |
/workspace/coverage/cover_reg_top/0.xbar_random.1619552714 |
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1878613177 |
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3322874891 |
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3770965776 |
/workspace/coverage/cover_reg_top/0.xbar_same_source.450086646 |
/workspace/coverage/cover_reg_top/0.xbar_smoke.1109926894 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3588216102 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3904129374 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2191441922 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1485158799 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1198685990 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2267295955 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2771233845 |
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2864740955 |
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1367463741 |
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.792440701 |
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3164637593 |
/workspace/coverage/cover_reg_top/1.chip_csr_rw.697815334 |
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2771090095 |
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1632424962 |
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.434058582 |
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1001560867 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1596988948 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2987035781 |
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1131509605 |
/workspace/coverage/cover_reg_top/1.xbar_error_random.3255858240 |
/workspace/coverage/cover_reg_top/1.xbar_random.3165689116 |
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1789387391 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1317100383 |
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1273501150 |
/workspace/coverage/cover_reg_top/1.xbar_same_source.233905461 |
/workspace/coverage/cover_reg_top/1.xbar_smoke.1151310962 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.904064835 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2698750153 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3293347951 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3809192148 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.505257886 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.190364974 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3545988845 |
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1990373152 |
/workspace/coverage/cover_reg_top/10.chip_csr_rw.587063677 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.429320522 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1862808983 |
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.878762323 |
/workspace/coverage/cover_reg_top/10.xbar_error_random.3959899420 |
/workspace/coverage/cover_reg_top/10.xbar_random.4249398140 |
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3261161646 |
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1593394095 |
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3054632828 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.1818467834 |
/workspace/coverage/cover_reg_top/10.xbar_smoke.343464461 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.231222316 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3696690088 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.335448478 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all.612276182 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.563215423 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2845933504 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.769878680 |
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1695438601 |
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2192798903 |
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1170619913 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3780875970 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1271179954 |
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.428548625 |
/workspace/coverage/cover_reg_top/11.xbar_error_random.1100862076 |
/workspace/coverage/cover_reg_top/11.xbar_random.3612427752 |
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.144346791 |
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1562524553 |
/workspace/coverage/cover_reg_top/11.xbar_same_source.2065066505 |
/workspace/coverage/cover_reg_top/11.xbar_smoke.581249952 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1259914556 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2711281861 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.846140126 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3156524998 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.112079557 |
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1042278316 |
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1375789511 |
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.561299168 |
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2834534128 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.91756550 |
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2998371324 |
/workspace/coverage/cover_reg_top/12.xbar_error_random.307495191 |
/workspace/coverage/cover_reg_top/12.xbar_random.2022520577 |
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2994205163 |
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2190074725 |
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.804294597 |
/workspace/coverage/cover_reg_top/12.xbar_same_source.1740784805 |
/workspace/coverage/cover_reg_top/12.xbar_smoke.3371063890 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2134197921 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2583270594 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3949665557 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1600117604 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.899289424 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2032476835 |
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3958657255 |
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3038588683 |
/workspace/coverage/cover_reg_top/13.chip_tl_errors.547022267 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3225043335 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2266249581 |
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.323860511 |
/workspace/coverage/cover_reg_top/13.xbar_error_random.4173527261 |
/workspace/coverage/cover_reg_top/13.xbar_random.1863191889 |
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2953886484 |
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1043176 |
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.696427761 |
/workspace/coverage/cover_reg_top/13.xbar_same_source.3441533894 |
/workspace/coverage/cover_reg_top/13.xbar_smoke.48213852 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3519385846 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.719194877 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4219631779 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all.248571457 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2849205796 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.888170221 |
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.202699815 |
/workspace/coverage/cover_reg_top/14.chip_csr_rw.4209948097 |
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3645687975 |
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1419462293 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1963329604 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1783447508 |
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2414058201 |
/workspace/coverage/cover_reg_top/14.xbar_error_random.255292397 |
/workspace/coverage/cover_reg_top/14.xbar_random.3415242378 |
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3607082686 |
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2339144817 |
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2973063331 |
/workspace/coverage/cover_reg_top/14.xbar_same_source.654725785 |
/workspace/coverage/cover_reg_top/14.xbar_smoke.2828218396 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2562627594 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2746873631 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3797470938 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all.2469808740 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1402692584 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.29839311 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4069864161 |
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2163243527 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.1317101508 |
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.297562073 |
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3078013079 |
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4262858760 |
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1593555062 |
/workspace/coverage/cover_reg_top/15.xbar_error_random.2292823640 |
/workspace/coverage/cover_reg_top/15.xbar_random.619647285 |
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/workspace/coverage/cover_reg_top/15.xbar_same_source.1753441256 |
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/workspace/coverage/cover_reg_top/16.chip_csr_rw.63098819 |
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3927957538 |
/workspace/coverage/cover_reg_top/16.chip_tl_errors.3430076271 |
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.62703154 |
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/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3272783867 |
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/workspace/coverage/cover_reg_top/19.xbar_stress_all.3971485547 |
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/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.3213855761 |
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/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.188736159 |
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/workspace/coverage/cover_reg_top/2.xbar_access_same_device.1294466163 |
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2522571585 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2475342271 |
/workspace/coverage/default/3.chip_tap_straps_dev.3534382206 |
/workspace/coverage/default/3.chip_tap_straps_prod.3358412047 |
/workspace/coverage/default/3.chip_tap_straps_rma.3158548166 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3475701244 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1966274789 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2625073628 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.858406247 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.929007891 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2141928601 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.842707158 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2389719125 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1646034217 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1666441738 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.68261221 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2864423447 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1281193374 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3706517279 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3396728371 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.112561589 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.326145235 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3352247814 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2350436870 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2496590792 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2216882198 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2020597550 |
/workspace/coverage/default/4.chip_tap_straps_prod.758973744 |
/workspace/coverage/default/4.chip_tap_straps_rma.2270973335 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4278443688 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1549353716 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352650410 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2058911568 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993110701 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.874011860 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.563842980 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1021883746 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1091476982 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4047592249 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2798156078 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282988939 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1135758547 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.845445180 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703474367 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3624482949 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2982678992 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1967231335 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1513550827 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3825313342 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3404879127 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4214088358 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2498396149 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2228982333 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101955591 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.823906552 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2728617206 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2927469777 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200678821 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.966121557 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.485845309 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.554475813 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411221485 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1580511421 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3192034559 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2518012179 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3374098861 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1196555874 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.760830376 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604420177 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2873618261 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133823229 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3943437327 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2829531898 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.911748369 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1994062292 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017083176 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3524707521 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3083384172 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.764575426 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3087571268 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3374818872 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.60660631 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1692889131 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032825009 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1108061000 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4204223187 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3682400741 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3852836973 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2457989290 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.859259763 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2412698516 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3644477437 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2068657061 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1802212896 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.281237119 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1617520592 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945385880 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3502996905 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2728311059 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369139993 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.457832282 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2811506616 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638237811 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1747851958 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.403795504 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1672797980 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3361965493 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1763774994 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.886813156 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.970786587 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3284369004 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3273094389 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1569046101 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224811571 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2941086343 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3266391851 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.335556445 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286377871 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2338026619 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695022898 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.201467615 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.973057228 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.383596148 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4260381370 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.4110568276 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2727276396 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.680590657 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1567605801 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1045669752 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3951310837 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3651099260 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1786151232 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.824949339 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3683843736 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.808174555 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3920463479 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2582677622 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.857992592 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3255882810 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2312910013 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3201761365 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4073515237 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3026208408 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1416003519 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T4 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1880255701 |
|
|
Jul 15 08:07:06 PM PDT 24 |
Jul 15 08:17:42 PM PDT 24 |
5781729864 ps |
T5 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2041240968 |
|
|
Jul 15 08:09:24 PM PDT 24 |
Jul 15 08:30:17 PM PDT 24 |
8122966292 ps |
T6 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2573263897 |
|
|
Jul 15 08:33:57 PM PDT 24 |
Jul 15 08:43:58 PM PDT 24 |
4961253330 ps |
T17 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.593818095 |
|
|
Jul 15 08:02:48 PM PDT 24 |
Jul 15 08:15:07 PM PDT 24 |
4668862456 ps |
T33 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3572262701 |
|
|
Jul 15 08:19:28 PM PDT 24 |
Jul 15 09:12:20 PM PDT 24 |
20815355488 ps |
T18 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.520153954 |
|
|
Jul 15 08:17:10 PM PDT 24 |
Jul 15 08:29:11 PM PDT 24 |
3767651696 ps |
T85 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3414484137 |
|
|
Jul 15 08:27:22 PM PDT 24 |
Jul 15 09:56:25 PM PDT 24 |
26804721348 ps |
T86 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4011605185 |
|
|
Jul 15 08:21:52 PM PDT 24 |
Jul 15 09:10:10 PM PDT 24 |
17098934072 ps |
T27 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2852558583 |
|
|
Jul 15 08:28:56 PM PDT 24 |
Jul 15 08:50:53 PM PDT 24 |
8142464968 ps |
T28 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3473101168 |
|
|
Jul 15 08:06:34 PM PDT 24 |
Jul 15 08:11:26 PM PDT 24 |
3337196960 ps |
T200 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1594989071 |
|
|
Jul 15 08:25:49 PM PDT 24 |
Jul 15 08:31:30 PM PDT 24 |
3197090734 ps |
T19 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1099469036 |
|
|
Jul 15 08:16:02 PM PDT 24 |
Jul 15 11:13:41 PM PDT 24 |
63820925854 ps |
T67 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1428746660 |
|
|
Jul 15 08:28:52 PM PDT 24 |
Jul 15 08:40:27 PM PDT 24 |
5305972504 ps |
T60 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2094482137 |
|
|
Jul 15 08:06:38 PM PDT 24 |
Jul 15 08:53:11 PM PDT 24 |
30759073746 ps |
T55 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1746779381 |
|
|
Jul 15 08:15:13 PM PDT 24 |
Jul 15 09:47:18 PM PDT 24 |
18322833824 ps |
T56 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.2849484876 |
|
|
Jul 15 08:12:15 PM PDT 24 |
Jul 15 09:11:37 PM PDT 24 |
15536746554 ps |
T178 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1701616435 |
|
|
Jul 15 08:22:55 PM PDT 24 |
Jul 15 08:31:43 PM PDT 24 |
4352219950 ps |
T390 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2612917020 |
|
|
Jul 15 08:23:48 PM PDT 24 |
Jul 15 08:27:49 PM PDT 24 |
2715135992 ps |
T126 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.3098872558 |
|
|
Jul 15 08:06:33 PM PDT 24 |
Jul 15 08:50:44 PM PDT 24 |
9495718488 ps |
T189 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3172134863 |
|
|
Jul 15 08:09:40 PM PDT 24 |
Jul 15 08:22:20 PM PDT 24 |
5212216066 ps |
T25 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.808688550 |
|
|
Jul 15 08:06:25 PM PDT 24 |
Jul 15 08:11:42 PM PDT 24 |
3885067010 ps |
T66 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4074257809 |
|
|
Jul 15 08:07:45 PM PDT 24 |
Jul 15 08:16:23 PM PDT 24 |
4442528812 ps |
T61 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2026201279 |
|
|
Jul 15 08:18:36 PM PDT 24 |
Jul 15 08:20:39 PM PDT 24 |
2442364073 ps |
T190 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2460474218 |
|
|
Jul 15 08:09:30 PM PDT 24 |
Jul 15 08:32:20 PM PDT 24 |
6515924290 ps |
T57 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1665288962 |
|
|
Jul 15 08:19:46 PM PDT 24 |
Jul 15 09:25:02 PM PDT 24 |
14840343517 ps |
T728 |
/workspace/coverage/default/2.chip_sw_aes_enc.1521421528 |
|
|
Jul 15 08:18:59 PM PDT 24 |
Jul 15 08:23:16 PM PDT 24 |
2790024404 ps |
T20 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.966543567 |
|
|
Jul 15 08:11:58 PM PDT 24 |
Jul 15 09:21:55 PM PDT 24 |
14810950804 ps |
T227 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3573012340 |
|
|
Jul 15 08:10:59 PM PDT 24 |
Jul 15 09:10:49 PM PDT 24 |
13942855215 ps |
T120 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1331651549 |
|
|
Jul 15 08:06:59 PM PDT 24 |
Jul 15 08:12:02 PM PDT 24 |
4763531384 ps |
T21 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1484083804 |
|
|
Jul 15 08:09:38 PM PDT 24 |
Jul 15 09:57:20 PM PDT 24 |
47791755721 ps |
T58 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3200007218 |
|
|
Jul 15 08:06:51 PM PDT 24 |
Jul 15 08:23:08 PM PDT 24 |
8270213670 ps |
T272 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1570727136 |
|
|
Jul 15 08:21:48 PM PDT 24 |
Jul 15 08:31:27 PM PDT 24 |
9319210745 ps |
T449 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.427089706 |
|
|
Jul 15 08:06:07 PM PDT 24 |
Jul 15 08:26:34 PM PDT 24 |
5569124810 ps |
T895 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2161480656 |
|
|
Jul 15 08:07:04 PM PDT 24 |
Jul 15 08:10:27 PM PDT 24 |
2104584610 ps |
T59 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2976065099 |
|
|
Jul 15 08:01:59 PM PDT 24 |
Jul 15 08:39:10 PM PDT 24 |
22979400696 ps |
T148 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2882110880 |
|
|
Jul 15 08:04:24 PM PDT 24 |
Jul 15 08:35:48 PM PDT 24 |
7799865240 ps |
T327 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3951310837 |
|
|
Jul 15 08:33:20 PM PDT 24 |
Jul 15 08:41:45 PM PDT 24 |
5551495010 ps |
T170 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1240986229 |
|
|
Jul 15 08:02:28 PM PDT 24 |
Jul 15 08:35:13 PM PDT 24 |
22272300012 ps |
T30 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.480257861 |
|
|
Jul 15 08:01:44 PM PDT 24 |
Jul 15 08:08:56 PM PDT 24 |
3165092520 ps |
T896 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3708015758 |
|
|
Jul 15 08:01:43 PM PDT 24 |
Jul 15 08:07:24 PM PDT 24 |
4899614500 ps |
T128 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.90932114 |
|
|
Jul 15 08:10:37 PM PDT 24 |
Jul 15 08:18:42 PM PDT 24 |
4771964282 ps |
T198 |
/workspace/coverage/default/2.chip_tap_straps_prod.4209058873 |
|
|
Jul 15 08:23:58 PM PDT 24 |
Jul 15 08:26:44 PM PDT 24 |
3150210142 ps |
T225 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.998220803 |
|
|
Jul 15 08:18:03 PM PDT 24 |
Jul 15 08:43:56 PM PDT 24 |
8753997928 ps |
T389 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2927845051 |
|
|
Jul 15 08:09:55 PM PDT 24 |
Jul 15 09:46:08 PM PDT 24 |
24420403320 ps |
T71 |
/workspace/coverage/default/2.chip_jtag_mem_access.1153646651 |
|
|
Jul 15 08:15:05 PM PDT 24 |
Jul 15 08:40:23 PM PDT 24 |
13880751848 ps |
T181 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1693118962 |
|
|
Jul 15 08:04:42 PM PDT 24 |
Jul 15 08:17:19 PM PDT 24 |
6435174040 ps |
T315 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101955591 |
|
|
Jul 15 08:31:55 PM PDT 24 |
Jul 15 08:38:00 PM PDT 24 |
3853979460 ps |
T316 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2353888347 |
|
|
Jul 15 08:17:06 PM PDT 24 |
Jul 15 08:30:57 PM PDT 24 |
6205728736 ps |
T317 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.3404329801 |
|
|
Jul 15 08:10:10 PM PDT 24 |
Jul 15 08:21:39 PM PDT 24 |
3865111654 ps |
T171 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2034003313 |
|
|
Jul 15 08:07:25 PM PDT 24 |
Jul 15 08:14:54 PM PDT 24 |
5476717802 ps |
T318 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.256244173 |
|
|
Jul 15 08:01:50 PM PDT 24 |
Jul 15 08:12:35 PM PDT 24 |
4164469968 ps |
T319 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2306237540 |
|
|
Jul 15 08:15:43 PM PDT 24 |
Jul 15 08:21:22 PM PDT 24 |
3275501088 ps |
T29 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2082392399 |
|
|
Jul 15 08:27:45 PM PDT 24 |
Jul 15 08:54:36 PM PDT 24 |
8356108944 ps |
T320 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3093118372 |
|
|
Jul 15 08:18:27 PM PDT 24 |
Jul 15 08:26:42 PM PDT 24 |
5145827218 ps |
T115 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3798753046 |
|
|
Jul 15 08:18:17 PM PDT 24 |
Jul 15 08:29:57 PM PDT 24 |
4125936868 ps |
T223 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2190041534 |
|
|
Jul 15 08:17:39 PM PDT 24 |
Jul 15 08:27:49 PM PDT 24 |
3932945406 ps |
T331 |
/workspace/coverage/default/0.chip_sw_example_rom.2269348171 |
|
|
Jul 15 08:00:05 PM PDT 24 |
Jul 15 08:02:04 PM PDT 24 |
2626070180 ps |
T84 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3394394333 |
|
|
Jul 15 08:17:14 PM PDT 24 |
Jul 15 11:55:41 PM PDT 24 |
78784888248 ps |
T173 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4204223187 |
|
|
Jul 15 08:27:32 PM PDT 24 |
Jul 15 08:34:58 PM PDT 24 |
6744385805 ps |
T199 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3589304327 |
|
|
Jul 15 08:16:30 PM PDT 24 |
Jul 15 08:18:30 PM PDT 24 |
2216198256 ps |
T111 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3468975138 |
|
|
Jul 15 08:22:03 PM PDT 24 |
Jul 15 08:27:55 PM PDT 24 |
2810928364 ps |
T897 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2020597550 |
|
|
Jul 15 08:25:31 PM PDT 24 |
Jul 15 08:36:28 PM PDT 24 |
4138228940 ps |
T228 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.368657883 |
|
|
Jul 15 08:19:53 PM PDT 24 |
Jul 15 08:54:33 PM PDT 24 |
10005753052 ps |
T205 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4231725443 |
|
|
Jul 15 08:02:13 PM PDT 24 |
Jul 15 11:53:15 PM PDT 24 |
79044579371 ps |
T62 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3851367203 |
|
|
Jul 15 07:55:54 PM PDT 24 |
Jul 15 08:09:19 PM PDT 24 |
8946404352 ps |
T121 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1070931390 |
|
|
Jul 15 08:10:57 PM PDT 24 |
Jul 15 08:20:02 PM PDT 24 |
6522127440 ps |
T172 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.4120111648 |
|
|
Jul 15 08:14:36 PM PDT 24 |
Jul 15 09:40:12 PM PDT 24 |
47778477628 ps |
T116 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2350436870 |
|
|
Jul 15 08:28:22 PM PDT 24 |
Jul 15 08:38:54 PM PDT 24 |
5014019880 ps |
T340 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2593714308 |
|
|
Jul 15 08:29:06 PM PDT 24 |
Jul 15 08:35:53 PM PDT 24 |
3838186740 ps |
T226 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1692889131 |
|
|
Jul 15 08:33:34 PM PDT 24 |
Jul 15 08:42:50 PM PDT 24 |
5333736152 ps |
T110 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2677843179 |
|
|
Jul 15 08:12:24 PM PDT 24 |
Jul 15 08:32:26 PM PDT 24 |
9045338895 ps |
T122 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4229312414 |
|
|
Jul 15 08:05:54 PM PDT 24 |
Jul 15 08:13:55 PM PDT 24 |
5805905280 ps |
T734 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.3596356551 |
|
|
Jul 15 08:20:02 PM PDT 24 |
Jul 15 08:50:06 PM PDT 24 |
8334911552 ps |
T361 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1549353716 |
|
|
Jul 15 08:29:57 PM PDT 24 |
Jul 15 08:45:04 PM PDT 24 |
6246213848 ps |
T221 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2708027653 |
|
|
Jul 15 08:17:39 PM PDT 24 |
Jul 15 08:34:25 PM PDT 24 |
5225562400 ps |
T362 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2674374857 |
|
|
Jul 15 08:28:32 PM PDT 24 |
Jul 15 08:39:27 PM PDT 24 |
4609889968 ps |
T157 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3273094389 |
|
|
Jul 15 08:33:25 PM PDT 24 |
Jul 15 08:38:18 PM PDT 24 |
3457836440 ps |
T735 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1186846293 |
|
|
Jul 15 08:17:29 PM PDT 24 |
Jul 15 08:24:57 PM PDT 24 |
3256252224 ps |
T143 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.235437328 |
|
|
Jul 15 08:11:58 PM PDT 24 |
Jul 15 08:16:28 PM PDT 24 |
3368646385 ps |
T346 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1743447061 |
|
|
Jul 15 08:10:02 PM PDT 24 |
Jul 15 08:20:24 PM PDT 24 |
4154542746 ps |
T898 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.681305025 |
|
|
Jul 15 08:27:31 PM PDT 24 |
Jul 15 08:32:42 PM PDT 24 |
2855742792 ps |
T154 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.384255206 |
|
|
Jul 15 08:21:57 PM PDT 24 |
Jul 15 08:31:40 PM PDT 24 |
4529795864 ps |
T899 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.170693893 |
|
|
Jul 15 08:25:33 PM PDT 24 |
Jul 15 08:35:49 PM PDT 24 |
3359490746 ps |
T744 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282988939 |
|
|
Jul 15 08:30:19 PM PDT 24 |
Jul 15 08:36:32 PM PDT 24 |
3518865116 ps |
T264 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2727276396 |
|
|
Jul 15 08:28:22 PM PDT 24 |
Jul 15 10:12:24 PM PDT 24 |
29101226560 ps |
T779 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3624482949 |
|
|
Jul 15 08:31:18 PM PDT 24 |
Jul 15 08:40:28 PM PDT 24 |
5046313476 ps |
T394 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2261396374 |
|
|
Jul 15 08:28:44 PM PDT 24 |
Jul 15 08:35:33 PM PDT 24 |
3621461944 ps |
T395 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1417892345 |
|
|
Jul 15 08:29:03 PM PDT 24 |
Jul 15 08:39:15 PM PDT 24 |
5330061304 ps |
T73 |
/workspace/coverage/default/4.chip_tap_straps_prod.758973744 |
|
|
Jul 15 08:25:40 PM PDT 24 |
Jul 15 08:45:33 PM PDT 24 |
13229285789 ps |
T691 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1994062292 |
|
|
Jul 15 08:32:10 PM PDT 24 |
Jul 15 08:41:06 PM PDT 24 |
4941604080 ps |
T174 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3936478265 |
|
|
Jul 15 08:17:27 PM PDT 24 |
Jul 15 08:49:13 PM PDT 24 |
20094891378 ps |
T420 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2233105465 |
|
|
Jul 15 08:20:50 PM PDT 24 |
Jul 15 08:25:46 PM PDT 24 |
2326114000 ps |
T900 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2691882568 |
|
|
Jul 15 08:29:22 PM PDT 24 |
Jul 15 08:46:35 PM PDT 24 |
10614446616 ps |
T901 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3609847195 |
|
|
Jul 15 08:22:14 PM PDT 24 |
Jul 15 08:33:58 PM PDT 24 |
4949206678 ps |
T344 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.976649408 |
|
|
Jul 15 08:19:09 PM PDT 24 |
Jul 15 08:34:52 PM PDT 24 |
5856284200 ps |
T259 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.63680004 |
|
|
Jul 15 08:25:40 PM PDT 24 |
Jul 15 08:31:46 PM PDT 24 |
2391577062 ps |
T745 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.842707158 |
|
|
Jul 15 08:32:06 PM PDT 24 |
Jul 15 08:39:39 PM PDT 24 |
4284140000 ps |
T537 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2730807201 |
|
|
Jul 15 08:17:07 PM PDT 24 |
Jul 15 08:22:32 PM PDT 24 |
2778562562 ps |
T229 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4244862850 |
|
|
Jul 15 08:04:13 PM PDT 24 |
Jul 15 08:39:38 PM PDT 24 |
9925739998 ps |
T736 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.4187863358 |
|
|
Jul 15 08:24:30 PM PDT 24 |
Jul 15 08:30:05 PM PDT 24 |
2506087586 ps |
T418 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2971553863 |
|
|
Jul 15 08:28:24 PM PDT 24 |
Jul 15 09:26:57 PM PDT 24 |
14179203885 ps |
T144 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.9476419 |
|
|
Jul 15 08:21:12 PM PDT 24 |
Jul 15 08:26:12 PM PDT 24 |
2840363428 ps |
T135 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2780563858 |
|
|
Jul 15 08:25:32 PM PDT 24 |
Jul 15 08:35:04 PM PDT 24 |
6210006788 ps |
T902 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.680590657 |
|
|
Jul 15 08:27:33 PM PDT 24 |
Jul 15 08:44:15 PM PDT 24 |
13058913696 ps |
T701 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4137062112 |
|
|
Jul 15 08:05:15 PM PDT 24 |
Jul 15 08:13:15 PM PDT 24 |
5264522968 ps |
T72 |
/workspace/coverage/default/1.chip_tap_straps_rma.1756164792 |
|
|
Jul 15 08:12:13 PM PDT 24 |
Jul 15 08:18:47 PM PDT 24 |
4640489828 ps |
T149 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3364752839 |
|
|
Jul 15 08:27:59 PM PDT 24 |
Jul 15 08:51:55 PM PDT 24 |
7753455088 ps |
T112 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.361610608 |
|
|
Jul 15 08:06:58 PM PDT 24 |
Jul 15 08:11:27 PM PDT 24 |
3273910231 ps |
T903 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3928934367 |
|
|
Jul 15 08:04:20 PM PDT 24 |
Jul 15 08:11:00 PM PDT 24 |
3368094856 ps |
T271 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2176091430 |
|
|
Jul 15 08:12:08 PM PDT 24 |
Jul 15 08:14:10 PM PDT 24 |
1728092264 ps |
T250 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3394054450 |
|
|
Jul 15 08:11:04 PM PDT 24 |
Jul 15 08:19:55 PM PDT 24 |
4546900116 ps |
T26 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2178806098 |
|
|
Jul 15 08:01:56 PM PDT 24 |
Jul 15 08:11:24 PM PDT 24 |
4382986124 ps |
T129 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3325104873 |
|
|
Jul 15 08:20:52 PM PDT 24 |
Jul 15 08:30:12 PM PDT 24 |
5766176712 ps |
T53 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1653705659 |
|
|
Jul 15 08:13:43 PM PDT 24 |
Jul 15 09:07:26 PM PDT 24 |
10651779796 ps |
T904 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1947171764 |
|
|
Jul 15 08:13:08 PM PDT 24 |
Jul 15 09:30:50 PM PDT 24 |
15522385072 ps |
T34 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3456164230 |
|
|
Jul 15 08:03:06 PM PDT 24 |
Jul 15 08:09:24 PM PDT 24 |
3688798592 ps |
T905 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2524769067 |
|
|
Jul 15 08:10:22 PM PDT 24 |
Jul 15 08:14:06 PM PDT 24 |
2962594264 ps |
T768 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2571101184 |
|
|
Jul 15 08:12:47 PM PDT 24 |
Jul 15 08:24:45 PM PDT 24 |
5678229902 ps |
T247 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1181565114 |
|
|
Jul 15 08:04:34 PM PDT 24 |
Jul 15 08:14:18 PM PDT 24 |
5922093448 ps |
T267 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1940998145 |
|
|
Jul 15 08:13:28 PM PDT 24 |
Jul 15 09:18:10 PM PDT 24 |
15204056908 ps |
T107 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1436346913 |
|
|
Jul 15 08:08:31 PM PDT 24 |
Jul 16 02:18:23 AM PDT 24 |
164164067960 ps |
T164 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4232844408 |
|
|
Jul 15 08:30:26 PM PDT 24 |
Jul 15 08:41:30 PM PDT 24 |
4561145192 ps |
T268 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.966121557 |
|
|
Jul 15 08:31:48 PM PDT 24 |
Jul 15 08:41:44 PM PDT 24 |
6278211560 ps |
T260 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2658566819 |
|
|
Jul 15 08:14:18 PM PDT 24 |
Jul 15 08:19:07 PM PDT 24 |
2684239800 ps |
T269 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352650410 |
|
|
Jul 15 08:29:57 PM PDT 24 |
Jul 15 08:36:47 PM PDT 24 |
4199521544 ps |
T117 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.130605282 |
|
|
Jul 15 08:12:38 PM PDT 24 |
Jul 15 08:24:01 PM PDT 24 |
4533723132 ps |
T270 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3159508541 |
|
|
Jul 15 08:08:25 PM PDT 24 |
Jul 15 08:16:08 PM PDT 24 |
6834460830 ps |
T224 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3350760663 |
|
|
Jul 15 08:04:13 PM PDT 24 |
Jul 15 08:22:30 PM PDT 24 |
5353066000 ps |
T239 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3813626568 |
|
|
Jul 15 08:03:55 PM PDT 24 |
Jul 15 09:44:45 PM PDT 24 |
47817790128 ps |
T244 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.223695837 |
|
|
Jul 15 08:09:11 PM PDT 24 |
Jul 15 08:15:14 PM PDT 24 |
4016537158 ps |
T906 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3415033117 |
|
|
Jul 15 08:19:56 PM PDT 24 |
Jul 15 08:26:22 PM PDT 24 |
3802856664 ps |
T108 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.998879645 |
|
|
Jul 15 08:14:25 PM PDT 24 |
Jul 15 08:45:58 PM PDT 24 |
9611168876 ps |
T353 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3282630475 |
|
|
Jul 15 08:16:38 PM PDT 24 |
Jul 15 08:27:17 PM PDT 24 |
4559468415 ps |
T179 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3683087069 |
|
|
Jul 15 08:21:43 PM PDT 24 |
Jul 15 08:31:46 PM PDT 24 |
4578282294 ps |
T288 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1567605801 |
|
|
Jul 15 08:28:37 PM PDT 24 |
Jul 15 08:38:01 PM PDT 24 |
3496133000 ps |
T289 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1514308773 |
|
|
Jul 15 08:03:56 PM PDT 24 |
Jul 15 08:23:32 PM PDT 24 |
10451539688 ps |
T290 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369139993 |
|
|
Jul 15 08:34:20 PM PDT 24 |
Jul 15 08:42:03 PM PDT 24 |
3632976770 ps |
T291 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2942175726 |
|
|
Jul 15 08:16:43 PM PDT 24 |
Jul 15 08:23:41 PM PDT 24 |
3681967424 ps |
T38 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2065308377 |
|
|
Jul 15 08:15:57 PM PDT 24 |
Jul 15 08:20:24 PM PDT 24 |
2637018602 ps |
T292 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.874011860 |
|
|
Jul 15 08:30:52 PM PDT 24 |
Jul 15 08:38:40 PM PDT 24 |
5560832956 ps |
T293 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.606863334 |
|
|
Jul 15 08:05:16 PM PDT 24 |
Jul 15 08:13:09 PM PDT 24 |
3290597834 ps |
T294 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3083384172 |
|
|
Jul 15 08:31:47 PM PDT 24 |
Jul 15 08:37:33 PM PDT 24 |
3638682490 ps |
T150 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2362855016 |
|
|
Jul 15 08:15:13 PM PDT 24 |
Jul 15 08:48:01 PM PDT 24 |
8099376894 ps |
T907 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.999601164 |
|
|
Jul 15 08:12:58 PM PDT 24 |
Jul 15 08:19:00 PM PDT 24 |
3142950388 ps |
T54 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3122549886 |
|
|
Jul 15 08:15:27 PM PDT 24 |
Jul 15 09:55:23 PM PDT 24 |
23658995638 ps |
T908 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2871091480 |
|
|
Jul 15 08:29:05 PM PDT 24 |
Jul 15 09:18:47 PM PDT 24 |
15787310896 ps |
T909 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3352247814 |
|
|
Jul 15 08:26:15 PM PDT 24 |
Jul 15 08:37:21 PM PDT 24 |
4332754946 ps |
T716 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3355385609 |
|
|
Jul 15 08:20:02 PM PDT 24 |
Jul 15 08:25:09 PM PDT 24 |
3392734928 ps |
T165 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3446052224 |
|
|
Jul 15 08:31:14 PM PDT 24 |
Jul 15 08:42:13 PM PDT 24 |
5610980728 ps |
T145 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.508430014 |
|
|
Jul 15 08:04:28 PM PDT 24 |
Jul 15 08:13:10 PM PDT 24 |
7825454040 ps |
T118 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1189597295 |
|
|
Jul 15 08:21:08 PM PDT 24 |
Jul 15 08:32:00 PM PDT 24 |
4842516402 ps |
T910 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1002838385 |
|
|
Jul 15 08:02:19 PM PDT 24 |
Jul 15 08:06:30 PM PDT 24 |
2595719344 ps |
T160 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2728617206 |
|
|
Jul 15 08:30:29 PM PDT 24 |
Jul 15 08:40:57 PM PDT 24 |
6184164478 ps |
T238 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4124181183 |
|
|
Jul 15 08:02:55 PM PDT 24 |
Jul 15 09:25:32 PM PDT 24 |
50096965310 ps |
T754 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.480585378 |
|
|
Jul 15 08:20:02 PM PDT 24 |
Jul 15 08:42:26 PM PDT 24 |
7608192596 ps |
T217 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2803075242 |
|
|
Jul 15 08:21:27 PM PDT 24 |
Jul 15 08:52:36 PM PDT 24 |
9435066356 ps |
T245 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1551192227 |
|
|
Jul 15 08:09:16 PM PDT 24 |
Jul 15 08:19:20 PM PDT 24 |
4544000120 ps |
T1 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2298576803 |
|
|
Jul 15 08:05:40 PM PDT 24 |
Jul 15 08:11:03 PM PDT 24 |
3619058882 ps |
T97 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.1436170962 |
|
|
Jul 15 08:13:40 PM PDT 24 |
Jul 15 08:25:36 PM PDT 24 |
4581715140 ps |
T98 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.916388840 |
|
|
Jul 15 08:17:15 PM PDT 24 |
Jul 15 08:19:27 PM PDT 24 |
2407943085 ps |
T99 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2465536286 |
|
|
Jul 15 08:25:09 PM PDT 24 |
Jul 15 09:30:57 PM PDT 24 |
17658651612 ps |
T100 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.991575427 |
|
|
Jul 15 08:05:13 PM PDT 24 |
Jul 15 08:22:09 PM PDT 24 |
7978691250 ps |
T101 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3314529196 |
|
|
Jul 15 08:04:23 PM PDT 24 |
Jul 15 08:10:17 PM PDT 24 |
3692042898 ps |
T102 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2944166831 |
|
|
Jul 15 08:05:25 PM PDT 24 |
Jul 15 08:11:18 PM PDT 24 |
2990520536 ps |
T103 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.777180717 |
|
|
Jul 15 08:14:44 PM PDT 24 |
Jul 15 08:17:59 PM PDT 24 |
2672144552 ps |
T104 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1309483145 |
|
|
Jul 15 08:19:07 PM PDT 24 |
Jul 15 08:42:24 PM PDT 24 |
12470744581 ps |
T105 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3533273730 |
|
|
Jul 15 08:24:30 PM PDT 24 |
Jul 15 08:35:48 PM PDT 24 |
4635983874 ps |
T31 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3082106871 |
|
|
Jul 15 08:26:48 PM PDT 24 |
Jul 15 08:32:54 PM PDT 24 |
6240828120 ps |
T222 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1156557027 |
|
|
Jul 15 08:14:36 PM PDT 24 |
Jul 15 08:29:22 PM PDT 24 |
5103446668 ps |
T180 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1915168453 |
|
|
Jul 15 08:22:10 PM PDT 24 |
Jul 15 08:36:42 PM PDT 24 |
7659265760 ps |
T325 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.764575426 |
|
|
Jul 15 08:32:18 PM PDT 24 |
Jul 15 08:40:18 PM PDT 24 |
4942077516 ps |
T2 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3517275485 |
|
|
Jul 15 08:07:20 PM PDT 24 |
Jul 15 08:14:23 PM PDT 24 |
7141733412 ps |
T440 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2331699160 |
|
|
Jul 15 08:28:39 PM PDT 24 |
Jul 15 09:08:29 PM PDT 24 |
11150849420 ps |
T45 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2207700253 |
|
|
Jul 15 08:04:16 PM PDT 24 |
Jul 15 08:08:42 PM PDT 24 |
3396628818 ps |
T240 |
/workspace/coverage/default/0.chip_sw_flash_init.4190707962 |
|
|
Jul 15 08:00:39 PM PDT 24 |
Jul 15 08:34:58 PM PDT 24 |
16587257160 ps |
T119 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2043798202 |
|
|
Jul 15 08:14:18 PM PDT 24 |
Jul 15 08:24:06 PM PDT 24 |
3917947892 ps |
T3 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3056431707 |
|
|
Jul 15 08:13:05 PM PDT 24 |
Jul 15 08:21:39 PM PDT 24 |
7459286744 ps |
T441 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1635493084 |
|
|
Jul 15 08:18:21 PM PDT 24 |
Jul 15 08:24:03 PM PDT 24 |
2973750040 ps |
T354 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1701680300 |
|
|
Jul 15 08:05:40 PM PDT 24 |
Jul 15 08:10:09 PM PDT 24 |
2960920841 ps |
T442 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1488904999 |
|
|
Jul 15 08:13:04 PM PDT 24 |
Jul 15 08:20:54 PM PDT 24 |
3736673766 ps |
T443 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3796525817 |
|
|
Jul 15 08:11:54 PM PDT 24 |
Jul 15 08:24:03 PM PDT 24 |
4587420492 ps |
T739 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4272903826 |
|
|
Jul 15 08:10:47 PM PDT 24 |
Jul 15 09:11:29 PM PDT 24 |
14812114863 ps |
T405 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4205711912 |
|
|
Jul 15 08:06:45 PM PDT 24 |
Jul 15 08:09:02 PM PDT 24 |
2305060222 ps |
T748 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2141928601 |
|
|
Jul 15 08:30:54 PM PDT 24 |
Jul 15 08:42:37 PM PDT 24 |
4419653856 ps |
T911 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1118164178 |
|
|
Jul 15 08:08:46 PM PDT 24 |
Jul 15 08:21:52 PM PDT 24 |
5072026924 ps |
T345 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.2784309883 |
|
|
Jul 15 08:04:31 PM PDT 24 |
Jul 15 08:20:19 PM PDT 24 |
5926211622 ps |
T912 |
/workspace/coverage/default/2.chip_tap_straps_dev.219680583 |
|
|
Jul 15 08:22:27 PM PDT 24 |
Jul 15 08:29:42 PM PDT 24 |
3551746315 ps |
T207 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1554849222 |
|
|
Jul 15 08:08:34 PM PDT 24 |
Jul 15 08:13:04 PM PDT 24 |
3228410525 ps |
T742 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1795882107 |
|
|
Jul 15 08:11:28 PM PDT 24 |
Jul 15 08:19:00 PM PDT 24 |
3862349304 ps |
T913 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3414046372 |
|
|
Jul 15 08:04:39 PM PDT 24 |
Jul 15 08:14:33 PM PDT 24 |
5348306152 ps |
T731 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1079581402 |
|
|
Jul 15 08:08:30 PM PDT 24 |
Jul 15 08:19:19 PM PDT 24 |
5621788160 ps |
T374 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.37421000 |
|
|
Jul 15 08:23:42 PM PDT 24 |
Jul 15 08:30:55 PM PDT 24 |
5361601304 ps |
T208 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1924401806 |
|
|
Jul 15 08:21:08 PM PDT 24 |
Jul 15 08:34:36 PM PDT 24 |
4906141715 ps |
T13 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.957099671 |
|
|
Jul 15 08:18:42 PM PDT 24 |
Jul 15 08:23:02 PM PDT 24 |
2547423564 ps |
T914 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3534737944 |
|
|
Jul 15 08:17:57 PM PDT 24 |
Jul 15 08:58:27 PM PDT 24 |
11137174567 ps |
T230 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2984778817 |
|
|
Jul 15 08:11:50 PM PDT 24 |
Jul 15 08:32:05 PM PDT 24 |
9193151136 ps |
T915 |
/workspace/coverage/default/0.rom_keymgr_functest.1519090765 |
|
|
Jul 15 08:05:46 PM PDT 24 |
Jul 15 08:17:42 PM PDT 24 |
4221407056 ps |
T916 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.443459734 |
|
|
Jul 15 08:11:39 PM PDT 24 |
Jul 15 08:21:31 PM PDT 24 |
5283130542 ps |
T182 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4130850740 |
|
|
Jul 15 08:05:11 PM PDT 24 |
Jul 15 08:10:07 PM PDT 24 |
3372490836 ps |
T307 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1534947221 |
|
|
Jul 15 08:19:12 PM PDT 24 |
Jul 15 08:24:05 PM PDT 24 |
2781936246 ps |
T83 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.2911624863 |
|
|
Jul 15 08:02:47 PM PDT 24 |
Jul 15 08:06:02 PM PDT 24 |
2487126292 ps |
T308 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4294078899 |
|
|
Jul 15 08:05:53 PM PDT 24 |
Jul 15 08:16:47 PM PDT 24 |
4902923024 ps |
T123 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3007616017 |
|
|
Jul 15 08:21:27 PM PDT 24 |
Jul 15 08:41:51 PM PDT 24 |
5915637380 ps |
T309 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.994469549 |
|
|
Jul 15 08:12:54 PM PDT 24 |
Jul 15 09:02:49 PM PDT 24 |
14538851528 ps |
T310 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3626747947 |
|
|
Jul 15 08:02:44 PM PDT 24 |
Jul 15 08:39:20 PM PDT 24 |
19685791851 ps |
T241 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2407860522 |
|
|
Jul 15 08:16:57 PM PDT 24 |
Jul 15 09:55:44 PM PDT 24 |
50032582518 ps |
T311 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.187222926 |
|
|
Jul 15 08:02:32 PM PDT 24 |
Jul 15 08:20:24 PM PDT 24 |
6285139059 ps |
T312 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.4116352358 |
|
|
Jul 15 08:27:41 PM PDT 24 |
Jul 15 08:36:25 PM PDT 24 |
5785307944 ps |
T403 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3834903607 |
|
|
Jul 15 08:15:13 PM PDT 24 |
Jul 15 10:15:27 PM PDT 24 |
23975753080 ps |
T917 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.210524349 |
|
|
Jul 15 08:15:40 PM PDT 24 |
Jul 15 08:22:11 PM PDT 24 |
5965770696 ps |
T161 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1569046101 |
|
|
Jul 15 08:32:39 PM PDT 24 |
Jul 15 08:40:20 PM PDT 24 |
5320932900 ps |
T130 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2743672788 |
|
|
Jul 15 08:16:52 PM PDT 24 |
Jul 15 08:27:58 PM PDT 24 |
5632883324 ps |
T918 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1304579910 |
|
|
Jul 15 08:21:00 PM PDT 24 |
Jul 15 08:30:33 PM PDT 24 |
3962410958 ps |
T919 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.632087029 |
|
|
Jul 15 08:03:39 PM PDT 24 |
Jul 15 08:13:57 PM PDT 24 |
8477525500 ps |
T920 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.1972678352 |
|
|
Jul 15 08:12:21 PM PDT 24 |
Jul 15 08:35:33 PM PDT 24 |
6545567382 ps |
T370 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3844715367 |
|
|
Jul 15 08:08:51 PM PDT 24 |
Jul 15 08:40:57 PM PDT 24 |
20269404334 ps |
T921 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3022265189 |
|
|
Jul 15 08:25:44 PM PDT 24 |
Jul 15 09:08:11 PM PDT 24 |
13627208760 ps |
T743 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.808174555 |
|
|
Jul 15 08:33:47 PM PDT 24 |
Jul 15 08:42:07 PM PDT 24 |
4614331606 ps |
T106 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.614123986 |
|
|
Jul 15 08:04:06 PM PDT 24 |
Jul 15 08:11:13 PM PDT 24 |
19636919420 ps |
T124 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.600072487 |
|
|
Jul 15 08:10:14 PM PDT 24 |
Jul 15 08:28:52 PM PDT 24 |
4683792320 ps |
T371 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3031324267 |
|
|
Jul 15 08:19:15 PM PDT 24 |
Jul 15 08:44:31 PM PDT 24 |
9594450202 ps |
T158 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1320327276 |
|
|
Jul 15 08:12:27 PM PDT 24 |
Jul 15 08:45:38 PM PDT 24 |
13697349880 ps |
T231 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1648264992 |
|
|
Jul 15 08:22:34 PM PDT 24 |
Jul 15 09:18:56 PM PDT 24 |
16103166520 ps |
T218 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.886813156 |
|
|
Jul 15 08:34:18 PM PDT 24 |
Jul 15 08:42:22 PM PDT 24 |
4661763640 ps |
T175 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2208058122 |
|
|
Jul 15 08:06:14 PM PDT 24 |
Jul 15 08:08:26 PM PDT 24 |
4213088397 ps |
T922 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.7063522 |
|
|
Jul 15 08:22:19 PM PDT 24 |
Jul 15 08:32:33 PM PDT 24 |
4598741360 ps |
T923 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.901617868 |
|
|
Jul 15 08:25:05 PM PDT 24 |
Jul 15 08:30:33 PM PDT 24 |
3110502426 ps |
T246 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2364396182 |
|
|
Jul 15 08:17:16 PM PDT 24 |
Jul 15 08:30:24 PM PDT 24 |
6606786600 ps |
T924 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2077763048 |
|
|
Jul 15 08:12:54 PM PDT 24 |
Jul 15 08:19:40 PM PDT 24 |
4247708888 ps |
T261 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1583059772 |
|
|
Jul 15 08:07:49 PM PDT 24 |
Jul 15 09:04:17 PM PDT 24 |
22805211985 ps |
T401 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.281237119 |
|
|
Jul 15 08:32:35 PM PDT 24 |
Jul 15 08:38:31 PM PDT 24 |
4300401506 ps |
T925 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1680379250 |
|
|
Jul 15 08:07:37 PM PDT 24 |
Jul 15 08:18:45 PM PDT 24 |
4779339790 ps |
T183 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2492642608 |
|
|
Jul 15 08:05:39 PM PDT 24 |
Jul 15 08:10:09 PM PDT 24 |
2845754769 ps |
T422 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945385880 |
|
|
Jul 15 08:34:50 PM PDT 24 |
Jul 15 08:41:42 PM PDT 24 |
3648097630 ps |
T407 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1292419036 |
|
|
Jul 15 08:20:50 PM PDT 24 |
Jul 15 08:43:11 PM PDT 24 |
10545539288 ps |
T804 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.4215633282 |
|
|
Jul 15 08:27:36 PM PDT 24 |
Jul 15 08:37:48 PM PDT 24 |
5441953360 ps |
T926 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1976924298 |
|
|
Jul 15 08:28:07 PM PDT 24 |
Jul 15 09:27:42 PM PDT 24 |
15608111478 ps |
T125 |
/workspace/coverage/default/2.chip_sw_edn_kat.1765312085 |
|
|
Jul 15 08:19:08 PM PDT 24 |
Jul 15 08:30:20 PM PDT 24 |
3349235594 ps |
T927 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.99484445 |
|
|
Jul 15 08:03:55 PM PDT 24 |
Jul 15 08:08:00 PM PDT 24 |
2698927524 ps |
T452 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2458852637 |
|
|
Jul 15 08:15:39 PM PDT 24 |
Jul 15 08:37:56 PM PDT 24 |
6672756610 ps |
T928 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3557227232 |
|
|
Jul 15 08:03:10 PM PDT 24 |
Jul 15 08:23:42 PM PDT 24 |
6488774596 ps |
T705 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1627988412 |
|
|
Jul 15 08:09:27 PM PDT 24 |
Jul 15 08:11:16 PM PDT 24 |
2232382907 ps |
T929 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3682400741 |
|
|
Jul 15 08:26:53 PM PDT 24 |
Jul 15 09:05:05 PM PDT 24 |
13079850080 ps |
T113 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3995179206 |
|
|
Jul 15 08:10:45 PM PDT 24 |
Jul 15 08:21:31 PM PDT 24 |
3991457337 ps |
T930 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1906691665 |
|
|
Jul 15 08:07:50 PM PDT 24 |
Jul 15 08:16:27 PM PDT 24 |
8738755877 ps |
T931 |
/workspace/coverage/default/0.rom_e2e_static_critical.1556939300 |
|
|
Jul 15 08:13:11 PM PDT 24 |
Jul 15 09:12:39 PM PDT 24 |
17382132940 ps |
T932 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1631441660 |
|
|
Jul 15 08:06:06 PM PDT 24 |
Jul 15 09:28:22 PM PDT 24 |
27816083800 ps |
T933 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4060329300 |
|
|
Jul 15 08:25:11 PM PDT 24 |
Jul 15 08:32:45 PM PDT 24 |
6585929000 ps |
T233 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1095154804 |
|
|
Jul 15 08:19:10 PM PDT 24 |
Jul 15 08:42:38 PM PDT 24 |
9854235318 ps |
T934 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2683172275 |
|
|
Jul 15 08:28:41 PM PDT 24 |
Jul 15 08:46:29 PM PDT 24 |
12698758893 ps |