Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total57200
Category 057200


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total57200
Severity 057200


Summary for Assertions
NUMBERPERCENT
Total Number572100.00
Uncovered142.45
Success55396.68
Failure00.00
Incomplete183.15
Without Attempts00.00
Excluded50.87


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmBusIntegrity_A 00128450310000
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A 0012845031000967
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLockstepResetCountAlertCheck_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexPcMismatchCheck_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexRfEccErrCheck_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexStoreRespIntgErrCheck_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheck_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.NoReadyValidNoGrant_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A 0051074615400998
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.ValidOPairedWithReadyI_A 00510746154000
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.NoReadyValidNoGrant_A 00510746154000
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmBusIntegrity_A 00510746154000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.top_earlgrey.scanmodeKnown 0051822318251822318200
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A 001575235138094800
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A 00128450310100
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A 001575235373700
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A 00128450310171600
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A 0012845031012776969000
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A 001575235138094800
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A 001575235138094800
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A 00128450310389180920276
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A 0012845031011938904015
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A 001284503101454099
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A 001284503101454099
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A 00128450310145400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A 001284503102620198
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A 001284503103578817600
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A 0012845031012776979900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0 0083170000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1 00175475100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit 0014883113863361000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv 0014883113863361000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse 0014883113848000600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A 0014883113810140600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A 0014883113822000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 001777540250976
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0017775402500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 0014883113824500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 00177754012500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113822200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A 001488311388222000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A 0014883113820600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113820600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754020600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754020600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113820600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A 001488311388533000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A 0014883113821300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A 001488311387651700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A 0014883113819100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113819100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754019100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754019100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113819100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A 001488311387459500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A 0014883113818700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113818700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754018700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754018700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113818700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A 001488311388657200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A 001488311389805200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A 0014883113824400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113824400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754024400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754024400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113824400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A 001488311388299200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A 0014883113820500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113820500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754020500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754020500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113820500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A 001488311386484900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A 0014883113816300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113816300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754016300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754016300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113816300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A 001488311388417500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A 001488311387804600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A 0014883113819200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113819200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754019200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754019100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113819200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A 001488311388847100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A 0014883113822100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113822100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754022100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754022100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113822100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A 001488311388537600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A 001488311388613400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A 001488311388841300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A 0014883113821900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A 001488311388591900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754021400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113821400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A 001488311387785200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A 0014883113819300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113819300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754019300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754019300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113819300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A 0014883113810044100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A 0014883113825000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113825000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754025000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754025000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113825100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A 001488311387970100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A 0014883113819700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113819700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754019700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754019700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113819700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A 001488311389492800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A 0014883113823500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113823500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754023500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754023500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113823500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A 001488311388921600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A 0014883113822100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113822100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754022100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754022100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113822200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A 001488311388248600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A 0014883113820400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113820400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754020400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754020400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113820500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A 001488311389241500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A 0014883113823000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113823000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754023000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754023000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113823000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A 001488311388362900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A 0014883113820700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113820700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754020700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754020700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113820700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A 001488311388180300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A 001777540155964600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A 0014883113820400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A 0014883113814804583900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014883113820400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00177754020400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00177754020400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014883113820400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse 0014883113815360400
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A 001575235138094800
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A 00510746154300
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A 0051074615424833351092
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A 0051074615465571241074
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A 0051074615444068704101996
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A 0051074615444068890001895
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A 005107461547800
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A 0051074615458700
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A 00510746154700
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A 005107461544250824500
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A 005107461543599521200
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A 005107461545918927900
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A 005107461544539989800
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 0051074615419600
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 0051074615419800
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs 005107461544246331000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs 005107461545918927900
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A 00510746154318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A 005100955599881292700
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A 00510746154432000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 00510746154432000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 00510746154432000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 00510746154432000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 00510746154432000
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A 0051074615450218100100
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A 00510746154519600
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A 0051074615451063252202994
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 005107461544800
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 005107461544800
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 001269336664800
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 005107461544800
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A 0051074615451063252202994
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit 005929510142350700
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv 005929510142350700
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse 005929510141782200
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A 005929510147826000
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A 005929510148044700
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 005929510145137400
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 005929510145137400
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 005929510142688600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 005929510142907300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0059295101459283244900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN 002903290300
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse 00592951014568500
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A 001013101300
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A 00510746154400
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A 0051074615450903439000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A 00510746154160568000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A 0051074615450903439000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A 00510746154160568000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A 001013101300
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete 0051074615451064007000
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit 0059295101420464300
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv 0059295101420464300
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse 0059295101414126100
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 002903290300
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse 005929510146338200
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A 00126933666300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit 00126933666530600
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv 00126933666530600
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse 00126933666383900
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 001013101300
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse 00126933666146700
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00564500
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 001028900
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 002231221400
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0068466600
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00483500
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0012110800
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 002227220900
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0013111600
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00735500
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 001119800
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 002703268600
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0012711600
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00775900
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0013412100
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 002704268800
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0032030800
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0015712900
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 002077204900
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0015612800
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 002068204000
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0015513800
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 00279532792400
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0014813100
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 00279512792200
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0046342100
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 00279682794000
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0046642400
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 00279662793800
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0071269100
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 002069204100
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0071269100
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 002066203800
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001013101300

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A 0012845031000967
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A 00128450310389180920276
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A 0012845031011938904015
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A 001284503101454099
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A 001284503101454099
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A 001284503102620198
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A 0012845031012776282303003
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 001777540250976
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A 0051074615424833351092
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A 0051074615465571241074
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A 0051074615444068704101996
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A 0051074615444068890001895
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A 0051074615400998
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A 0051074615451063252202994
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A 0051074615451063252202994

Assertions Excluded:
ASSERTIONSCATEGORYSEVERITYEXCLUSIONSRC
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded

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