Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	445	1			T255	1		T532	1		T457	1
all_values[1]	479	1			T255	1		T127	1		T457	4
all_values[2]	457	1			T255	1		T549	1		T457	2
all_values[3]	507	1			T457	3		T458	2		T463	7
all_values[4]	449	1			T532	1		T549	1		T457	4
all_values[5]	453	1			T255	1		T127	1		T538	1
all_values[6]	438	1			T457	1		T458	4		T463	5
all_values[7]	467	1			T255	1		T532	1		T458	2
all_values[8]	496	1			T127	1		T457	4		T458	4
all_values[9]	463	1			T457	1		T458	7		T540	1
all_values[10]	496	1			T549	1		T457	1		T458	7
all_values[11]	484	1			T532	1		T457	3		T458	3
all_values[12]	478	1			T255	1		T457	4		T458	4
all_values[13]	487	1			T255	1		T532	2		T457	2
all_values[14]	491	1			T127	1		T532	1		T457	2
all_values[15]	485	1			T532	1		T549	1		T457	3
all_values[16]	471	1			T127	1		T457	1		T458	3
all_values[17]	481	1			T532	1		T549	1		T457	5
all_values[18]	445	1			T538	1		T549	1		T457	1
all_values[19]	478	1			T457	2		T458	9		T463	3
all_values[20]	489	1			T532	1		T457	4		T458	5
all_values[21]	537	1			T538	1		T549	2		T858	1
all_values[22]	438	1			T549	1		T457	3		T458	1
all_values[23]	453	1			T457	3		T458	4		T463	3
all_values[24]	460	1			T457	4		T458	1		T463	6
all_values[25]	490	1			T549	1		T858	1		T457	3
all_values[26]	463	1			T532	2		T549	1		T457	2
all_values[27]	523	1			T457	3		T458	1		T463	2
all_values[28]	499	1			T532	1		T549	2		T457	2
all_values[29]	492	1			T532	1		T457	2		T458	3
all_values[30]	494	1			T127	1		T549	2		T457	3
all_values[31]	456	1			T532	3		T457	4		T463	1
all_values[32]	488	1			T457	4		T458	2		T463	2
all_values[33]	453	1			T549	1		T457	2		T458	2
all_values[34]	459	1			T532	1		T457	2		T458	2
all_values[35]	459	1			T532	2		T538	1		T549	1
all_values[36]	480	1			T457	1		T458	3		T541	1
all_values[37]	452	1			T457	2		T458	7		T463	2
all_values[38]	495	1			T457	2		T458	3		T540	1
all_values[39]	468	1			T458	1		T463	1		T850	1
all_values[40]	471	1			T538	1		T457	5		T458	6
all_values[41]	491	1			T532	1		T457	1		T463	3
all_values[42]	461	1			T457	1		T458	4		T463	3
all_values[43]	473	1			T127	1		T549	1		T457	1
all_values[44]	491	1			T457	1		T458	3		T541	1
all_values[45]	484	1			T532	2		T538	1		T457	2
all_values[46]	488	1			T255	1		T532	1		T549	1
all_values[47]	479	1			T255	1		T458	4		T463	1
all_values[48]	502	1			T457	3		T458	2		T541	1
all_values[49]	472	1			T127	1		T457	2		T458	5