Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3322	1			T78	2		T532	4		T457	28
all_values[1]	3430	1			T78	3		T532	6		T457	28
all_values[2]	3411	1			T78	5		T532	9		T457	27
all_values[3]	3396	1			T78	3		T532	10		T457	28
all_values[4]	3353	1			T532	7		T457	23		T458	30
all_values[5]	3312	1			T78	3		T532	4		T457	26
all_values[6]	3370	1			T532	5		T457	21		T458	33
all_values[7]	3434	1			T78	2		T532	6		T457	32
all_values[8]	3424	1			T532	6		T457	16		T458	24
all_values[9]	3286	1			T78	3		T532	5		T457	26
all_values[10]	3396	1			T78	2		T532	8		T457	23
all_values[11]	3423	1			T532	12		T457	27		T458	26
all_values[12]	3474	1			T78	3		T532	8		T457	26
all_values[13]	3462	1			T78	2		T532	3		T457	26
all_values[14]	3402	1			T78	2		T532	7		T457	29
all_values[15]	3393	1			T78	1		T532	11		T457	34
all_values[16]	3500	1			T78	5		T532	3		T457	25
all_values[17]	3418	1			T78	1		T532	6		T457	29
all_values[18]	3399	1			T78	2		T532	7		T457	29
all_values[19]	3371	1			T78	3		T532	6		T457	24
all_values[20]	3308	1			T78	3		T532	7		T457	29
all_values[21]	3385	1			T78	1		T532	2		T457	19
all_values[22]	3296	1			T78	1		T532	6		T457	29
all_values[23]	3489	1			T78	4		T532	4		T457	16
all_values[24]	3480	1			T78	5		T532	7		T457	35
all_values[25]	3321	1			T78	2		T532	9		T457	32
all_values[26]	3488	1			T78	4		T532	8		T457	27
all_values[27]	3389	1			T78	4		T532	8		T457	24
all_values[28]	3379	1			T78	3		T532	2		T457	30
all_values[29]	3315	1			T78	1		T532	9		T457	29
all_values[30]	3386	1			T78	2		T532	6		T457	27
all_values[31]	3501	1			T78	3		T532	3		T457	19
all_values[32]	3240	1			T78	3		T532	11		T457	27
all_values[33]	3448	1			T78	2		T532	3		T457	26
all_values[34]	3510	1			T78	10		T532	6		T457	29
all_values[35]	3379	1			T78	2		T532	2		T457	26
all_values[36]	3402	1			T78	4		T532	11		T457	33
all_values[37]	3371	1			T78	2		T532	4		T457	26
all_values[38]	3436	1			T78	4		T532	5		T457	25
all_values[39]	3388	1			T78	4		T532	7		T457	19
all_values[40]	3491	1			T532	11		T457	30		T458	25
all_values[41]	3386	1			T78	2		T532	9		T457	22
all_values[42]	3356	1			T78	2		T532	5		T457	29
all_values[43]	3400	1			T78	1		T532	7		T457	29
all_values[44]	3436	1			T78	4		T532	4		T457	31
all_values[45]	3372	1			T78	4		T532	4		T457	38
all_values[46]	3467	1			T78	3		T532	4		T457	17
all_values[47]	3394	1			T78	2		T532	6		T457	24
all_values[48]	3393	1			T78	2		T532	5		T457	18
all_values[49]	3451	1			T78	1		T532	8		T457	26
all_values[50]	3414	1			T78	1		T532	7		T457	25
all_values[51]	3390	1			T78	4		T532	7		T457	32
all_values[52]	3429	1			T78	2		T532	3		T457	24
all_values[53]	3339	1			T532	7		T457	20		T458	26
all_values[54]	3408	1			T78	3		T532	7		T457	27
all_values[55]	3383	1			T78	3		T532	6		T457	29
all_values[56]	3273	1			T78	2		T532	5		T457	37
all_values[57]	3280	1			T78	3		T532	6		T457	29
all_values[58]	3451	1			T78	2		T532	11		T457	28
all_values[59]	3404	1			T78	2		T532	3		T457	19
all_values[60]	3463	1			T78	2		T532	4		T457	38
all_values[61]	3387	1			T78	3		T532	6		T457	27
all_values[62]	3457	1			T78	7		T532	6		T457	27
all_values[63]	3310	1			T532	6		T457	23		T458	29