Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 3797782 1 T78 1625 T79 7519 T80 5688
values[2] 761542 1 T78 163 T79 2075 T80 890
values[3] 106249 1 T78 4 T79 424 T80 1
values[4] 55945 1 T78 1 T79 191 T673 3
values[5] 38070 1 T78 3 T79 118 T673 3
values[6] 28915 1 T78 2 T79 50 T673 3
values[7] 23535 1 T78 1 T79 41 T673 3
values[8] 19975 1 T78 2 T79 27 T673 3
values[9] 17249 1 T79 13 T673 3 T82 36
values[10] 15925 1 T79 9 T673 3 T82 46
values[11] 15211 1 T79 12 T673 3 T82 21
values[12] 14417 1 T79 9 T673 3 T82 28
values[13] 13702 1 T79 5 T673 3 T82 16
values[14] 12810 1 T79 6 T673 3 T82 9
values[15] 12231 1 T79 5 T673 3 T82 13
values[16] 11986 1 T79 6 T673 3 T82 21
values[17] 11508 1 T79 7 T673 3 T82 20
values[18] 11104 1 T79 5 T673 3 T82 12
values[19] 10765 1 T79 10 T673 3 T82 6
values[20] 10272 1 T79 5 T673 3 T82 7
values[21] 10113 1 T79 12 T673 3 T82 10
values[22] 9629 1 T79 8 T673 3 T82 11
values[23] 9634 1 T79 9 T673 3 T82 19
values[24] 8996 1 T79 2 T673 3 T82 11
values[25] 8901 1 T79 2 T673 3 T82 14
values[26] 8815 1 T79 3 T673 3 T82 8
values[27] 8396 1 T79 6 T673 3 T82 16
values[28] 7913 1 T79 8 T673 4 T82 10
values[29] 7118 1 T79 4 T673 3 T82 13
values[30] 6791 1 T79 3 T673 3 T82 10
values[31] 6324 1 T79 2 T673 3 T82 13
values[32] 5758 1 T79 2 T673 3 T82 7
values[33] 5430 1 T79 4 T673 3 T82 17
values[34] 5201 1 T79 6 T673 3 T82 14
values[35] 4630 1 T79 6 T673 3 T82 14
values[36] 4460 1 T79 6 T673 3 T82 10
values[37] 4147 1 T79 3 T673 3 T82 10
values[38] 4062 1 T79 3 T673 3 T82 12
values[39] 3814 1 T79 3 T673 3 T82 7
values[40] 3651 1 T79 1 T673 3 T82 12
values[41] 3555 1 T79 1 T673 3 T82 19
values[42] 3467 1 T79 2 T673 3 T82 13
values[43] 3361 1 T79 1 T673 3 T82 22
values[44] 3261 1 T79 2 T673 3 T82 14
values[45] 3319 1 T79 7 T673 3 T82 10
values[46] 3148 1 T79 5 T673 3 T82 9
values[47] 3083 1 T79 1 T673 3 T82 19
values[48] 3099 1 T79 2 T673 3 T82 12
values[49] 3056 1 T79 1 T673 3 T82 14
values[50] 3031 1 T79 1 T673 3 T82 10
values[51] 3075 1 T79 3 T673 3 T82 11
values[52] 2932 1 T79 2 T673 3 T82 8
values[53] 2829 1 T79 1 T673 3 T82 10
values[54] 2766 1 T79 2 T673 3 T82 5
values[55] 2703 1 T79 3 T673 3 T82 8
values[56] 2656 1 T79 5 T673 3 T82 5
values[57] 2567 1 T79 1 T673 3 T82 5
values[58] 2562 1 T79 1 T673 3 T82 12
values[59] 2498 1 T79 4 T673 3 T82 20
values[60] 2529 1 T79 9 T673 3 T82 14
values[61] 2812 1 T79 9 T673 3 T82 12
values[62] 4053 1 T79 9 T673 3 T82 20
values[63] 10759 1 T79 4 T673 4 T82 64
values[64] 225168 1 T79 5 T673 466 T82 113


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 4870627 1 T78 3292 T79 9418 T80 6543
values[2] 834200 1 T78 549 T79 1761 T80 841
values[3] 83725 1 T78 31 T79 224 T80 29
values[4] 14768 1 T78 3 T79 10 T80 5
values[5] 5676 1 T78 3 T79 1 T80 1
values[6] 3446 1 T78 3 T673 3 T82 13
values[7] 2641 1 T78 4 T673 1 T82 4
values[8] 2168 1 T78 3 T673 1 T82 2
values[9] 1942 1 T78 4 T673 1 T513 2
values[10] 1690 1 T78 2 T673 1 T513 1
values[11] 1489 1 T78 2 T673 1 T513 2
values[12] 1365 1 T78 2 T673 1 T513 1
values[13] 1263 1 T78 2 T673 1 T513 1
values[14] 1172 1 T78 2 T673 1 T513 1
values[15] 980 1 T78 2 T673 1 T513 1
values[16] 925 1 T78 2 T673 1 T513 1
values[17] 848 1 T78 2 T673 1 T513 1
values[18] 864 1 T78 2 T673 1 T513 1
values[19] 780 1 T78 2 T673 1 T513 1
values[20] 781 1 T78 3 T673 1 T513 1
values[21] 733 1 T78 2 T673 1 T513 1
values[22] 724 1 T78 2 T673 1 T513 1
values[23] 718 1 T78 1 T673 1 T513 1
values[24] 719 1 T78 1 T673 1 T513 1
values[25] 628 1 T78 2 T673 1 T513 1
values[26] 623 1 T78 2 T673 1 T513 1
values[27] 571 1 T78 2 T673 1 T513 1
values[28] 581 1 T78 2 T673 1 T513 1
values[29] 580 1 T78 3 T673 1 T513 1
values[30] 544 1 T78 2 T673 1 T513 1
values[31] 536 1 T78 2 T673 1 T513 1
values[32] 555 1 T78 2 T673 1 T513 1
values[33] 474 1 T78 2 T673 1 T513 1
values[34] 469 1 T78 2 T673 1 T513 1
values[35] 454 1 T78 2 T673 1 T513 1
values[36] 435 1 T78 4 T673 1 T513 1
values[37] 460 1 T78 2 T673 1 T513 1
values[38] 470 1 T78 2 T673 1 T513 1
values[39] 429 1 T78 2 T673 1 T513 1
values[40] 445 1 T78 2 T673 1 T513 1
values[41] 419 1 T78 2 T673 1 T513 1
values[42] 410 1 T78 2 T673 1 T513 1
values[43] 423 1 T78 2 T673 1 T513 1
values[44] 411 1 T78 2 T673 1 T513 1
values[45] 375 1 T78 2 T673 1 T513 1
values[46] 357 1 T78 2 T673 1 T513 1
values[47] 397 1 T78 2 T673 1 T513 1
values[48] 369 1 T78 2 T673 1 T513 1
values[49] 375 1 T78 2 T673 1 T513 1
values[50] 399 1 T78 2 T673 1 T513 1
values[51] 421 1 T78 2 T673 1 T513 1
values[52] 357 1 T78 2 T673 1 T513 1
values[53] 388 1 T78 2 T673 1 T513 1
values[54] 374 1 T78 2 T673 1 T513 1
values[55] 376 1 T78 1 T673 1 T513 1
values[56] 340 1 T78 1 T673 1 T513 1
values[57] 374 1 T78 2 T673 1 T513 1
values[58] 352 1 T78 2 T673 1 T513 1
values[59] 360 1 T78 2 T673 1 T513 1
values[60] 371 1 T78 2 T673 1 T513 1
values[61] 427 1 T78 2 T673 1 T513 1
values[62] 621 1 T673 1 T513 1 T512 19
values[63] 2377 1 T673 1 T513 1 T512 46
values[64] 24283 1 T673 217 T513 155 T512 64


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 556639 1 T78 91 T79 579 T80 709
values[2] 2734364 1 T78 1471 T79 4178 T80 5435
values[3] 1214056 1 T78 159 T79 4279 T80 903
values[4] 148614 1 T78 10 T79 482 T80 3
values[5] 76859 1 T78 2 T79 294 T673 3
values[6] 50306 1 T79 194 T673 3 T82 191
values[7] 35838 1 T79 133 T673 3 T82 163
values[8] 28576 1 T79 112 T673 3 T82 120
values[9] 24330 1 T79 80 T673 3 T82 90
values[10] 21599 1 T79 44 T673 3 T82 94
values[11] 19780 1 T79 26 T673 3 T82 72
values[12] 18133 1 T79 7 T673 3 T82 55
values[13] 17234 1 T79 8 T673 3 T82 62
values[14] 15503 1 T79 8 T673 3 T82 35
values[15] 14958 1 T79 8 T673 3 T82 20
values[16] 14573 1 T79 4 T673 3 T82 18
values[17] 13948 1 T79 4 T673 3 T82 17
values[18] 13462 1 T79 6 T673 3 T82 18
values[19] 13034 1 T79 5 T673 3 T82 11
values[20] 12380 1 T79 16 T673 3 T82 14
values[21] 12090 1 T79 21 T673 3 T82 19
values[22] 11743 1 T79 12 T673 3 T82 7
values[23] 11170 1 T79 8 T673 3 T82 14
values[24] 10622 1 T79 7 T673 3 T82 13
values[25] 10205 1 T79 3 T673 3 T82 17
values[26] 9672 1 T79 4 T673 3 T82 6
values[27] 9166 1 T79 7 T673 3 T82 8
values[28] 8457 1 T79 5 T673 3 T82 14
values[29] 8124 1 T79 8 T673 3 T82 11
values[30] 7977 1 T79 4 T673 3 T82 10
values[31] 7245 1 T79 6 T673 3 T82 14
values[32] 6616 1 T79 5 T673 3 T82 19
values[33] 6193 1 T79 7 T673 3 T82 17
values[34] 5660 1 T79 3 T673 3 T82 16
values[35] 5437 1 T79 2 T673 3 T82 24
values[36] 5197 1 T79 2 T673 3 T82 14
values[37] 4844 1 T79 3 T673 3 T82 15
values[38] 4454 1 T79 1 T673 3 T82 7
values[39] 4308 1 T79 1 T673 4 T82 8
values[40] 4132 1 T79 1 T673 3 T82 10
values[41] 3972 1 T79 2 T673 3 T82 14
values[42] 3842 1 T79 3 T673 3 T82 12
values[43] 3718 1 T79 1 T673 3 T82 17
values[44] 3684 1 T79 1 T673 3 T82 11
values[45] 3557 1 T79 2 T673 3 T82 12
values[46] 3542 1 T79 3 T673 3 T82 16
values[47] 3476 1 T79 2 T673 3 T82 12
values[48] 3534 1 T79 1 T673 3 T82 16
values[49] 3391 1 T79 1 T673 3 T82 7
values[50] 3347 1 T79 4 T673 3 T82 11
values[51] 3347 1 T79 4 T673 3 T82 13
values[52] 3279 1 T79 2 T673 3 T82 7
values[53] 3223 1 T79 3 T673 3 T82 11
values[54] 3149 1 T79 4 T673 3 T82 12
values[55] 3051 1 T79 2 T673 3 T82 9
values[56] 2990 1 T79 7 T673 3 T82 10
values[57] 2923 1 T79 2 T673 3 T82 12
values[58] 2704 1 T79 1 T673 3 T82 14
values[59] 2809 1 T79 3 T673 3 T82 6
values[60] 2684 1 T79 3 T673 3 T82 7
values[61] 2977 1 T79 9 T673 3 T82 17
values[62] 3925 1 T79 4 T673 3 T82 37
values[63] 9351 1 T79 6 T673 3 T82 78
values[64] 221520 1 T79 3 T673 555 T82 123

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